Fundamental logics based on two phase clocked adiabatic static CMOS logic

Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

This paper demonstrates some fundamental logic gates employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We design and simulate NOT, NAND, NOR, and XOR logic gates oy the basis oy the 2PASCL topology using SPICE implemented using 0.18 μm CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. Froy the simulation results, we find that 2PASCL inverter logic can save up to 97% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 10 to 100 MHz. Further. The power dissipation i. The lowest when compared with other proposed simple adiabatic logic inverters. 2PASCL also achieve. The highest fan-out performance. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

Original languageEnglish
Title of host publication2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009
Pages503-506
Number of pages4
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009 - Yasmine Hammamet
Duration: 13 Dec 200916 Dec 2009

Other

Other2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009
CityYasmine Hammamet
Period13/12/0916/12/09

Fingerprint

Logic gates
Digital devices
Smart sensors
Smart cards
Logic circuits
SPICE
Radio frequency identification (RFID)
Fans
Energy dissipation
Topology
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Nayan, N. A., Takahashi, Y., & Sekine, T. (2009). Fundamental logics based on two phase clocked adiabatic static CMOS logic. In 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009 (pp. 503-506). [5410880] https://doi.org/10.1109/ICECS.2009.5410880

Fundamental logics based on two phase clocked adiabatic static CMOS logic. / Nayan, Nazrul Anuar; Takahashi, Yasuhiro; Sekine, Toshikazu.

2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. 2009. p. 503-506 5410880.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nayan, NA, Takahashi, Y & Sekine, T 2009, Fundamental logics based on two phase clocked adiabatic static CMOS logic. in 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009., 5410880, pp. 503-506, 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, Yasmine Hammamet, 13/12/09. https://doi.org/10.1109/ICECS.2009.5410880
Nayan NA, Takahashi Y, Sekine T. Fundamental logics based on two phase clocked adiabatic static CMOS logic. In 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. 2009. p. 503-506. 5410880 https://doi.org/10.1109/ICECS.2009.5410880
Nayan, Nazrul Anuar ; Takahashi, Yasuhiro ; Sekine, Toshikazu. / Fundamental logics based on two phase clocked adiabatic static CMOS logic. 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. 2009. pp. 503-506
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