FPGA implementation of an optimized coefficients pulse? Shaping FIR filters

Mohamed Almahdi Eshtawie, Masuri Othman

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    This paper presents the design and FPGA implementation for different order pulse shaping finite impulse response (FIR) filters. In this paper, the coefficients of the implemented filters have been modified with an optimization algorithm proposed in an earlier work. The use of this algorithm results in reducing the number of non-zero coefficients used to represent the filter's frequency response. Reducing the number of non-zero coefficients optimizes the implementation process especially when dealing with high order filters and when using lookup table (LUT) based techniques such as distributed arithmetic (DA). The designs have been downloaded to Xilinx Virtex-II FPGA and encouraging results were obtained. Hence, high-speed multiplierless design with a minimized number of arithmetic operations for different order pulse shaping FIR filters is achieved.

    Original languageEnglish
    Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
    Pages454-458
    Number of pages5
    DOIs
    Publication statusPublished - 2006
    Event2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006 - Kuala Lumpur
    Duration: 29 Nov 20061 Dec 2006

    Other

    Other2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006
    CityKuala Lumpur
    Period29/11/061/12/06

    Fingerprint

    FIR filters
    Field programmable gate arrays (FPGA)
    Pulse shaping
    Table lookup
    Frequency response

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Eshtawie, M. A., & Othman, M. (2006). FPGA implementation of an optimized coefficients pulse? Shaping FIR filters. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 454-458). [4266652] https://doi.org/10.1109/SMELEC.2006.381102

    FPGA implementation of an optimized coefficients pulse? Shaping FIR filters. / Eshtawie, Mohamed Almahdi; Othman, Masuri.

    IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. p. 454-458 4266652.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Eshtawie, MA & Othman, M 2006, FPGA implementation of an optimized coefficients pulse? Shaping FIR filters. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 4266652, pp. 454-458, 2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006, Kuala Lumpur, 29/11/06. https://doi.org/10.1109/SMELEC.2006.381102
    Eshtawie MA, Othman M. FPGA implementation of an optimized coefficients pulse? Shaping FIR filters. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. p. 454-458. 4266652 https://doi.org/10.1109/SMELEC.2006.381102
    Eshtawie, Mohamed Almahdi ; Othman, Masuri. / FPGA implementation of an optimized coefficients pulse? Shaping FIR filters. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. pp. 454-458
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