FPGA-based implementation of a new phaseto-sine amplitude conversion architecture

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

The classical structure of linear interpolationbased phase-to-sine mapper (PSM) consists of at least two ROMs for polynomial coefficient storage. Other architectures may include extra ROM for storing residual errors. However, ROMs dissipate high power and occupy a significant amount of the die area. This study presents a new technique that eliminates the ROM by including the computation of segment initial coefficients in the hardware. Therefore, it becomes possible to trim down noticeable hardware resources. The proposed direct digital frequency synthesizer (DDFS) architecture has been encoded in VHDL and synthesized with Quartus II software. Post simulation results show that the proposed design is capable of achieving the theoretical spurious-free dynamic range (SFDR) upper bound when optimal polynomial coefficients are considered. For 32 piecewise linear segments, the SFDR of the synthesized sinusoid is 84.15 dBc. A ROM compression ratio of 597.3:1 was also achieved. The performance of the DDFS is compared with previously presented DDFS techniques and the results show that the proposed design has advantages of high ROM compression ratio and low hardware complexity.

Original languageEnglish
Pages (from-to)103-108
Number of pages6
JournalElektronika ir Elektrotechnika
Volume19
Issue number10
DOIs
Publication statusPublished - 2013

Fingerprint

ROM
Field programmable gate arrays (FPGA)
Frequency synthesizers
Hardware
Polynomials
Computer hardware description languages

Keywords

  • DDS
  • Direct digital frequency synthesizer
  • Phase to sine amplitude conversion
  • Piecewise linear approximation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

FPGA-based implementation of a new phaseto-sine amplitude conversion architecture. / Omran, Q. K.; Islam, Mohammad Tariqul; Misran, Norbahiah.

In: Elektronika ir Elektrotechnika, Vol. 19, No. 10, 2013, p. 103-108.

Research output: Contribution to journalArticle

@article{17e3c80afbd24560bf7b339dbff8046f,
title = "FPGA-based implementation of a new phaseto-sine amplitude conversion architecture",
abstract = "The classical structure of linear interpolationbased phase-to-sine mapper (PSM) consists of at least two ROMs for polynomial coefficient storage. Other architectures may include extra ROM for storing residual errors. However, ROMs dissipate high power and occupy a significant amount of the die area. This study presents a new technique that eliminates the ROM by including the computation of segment initial coefficients in the hardware. Therefore, it becomes possible to trim down noticeable hardware resources. The proposed direct digital frequency synthesizer (DDFS) architecture has been encoded in VHDL and synthesized with Quartus II software. Post simulation results show that the proposed design is capable of achieving the theoretical spurious-free dynamic range (SFDR) upper bound when optimal polynomial coefficients are considered. For 32 piecewise linear segments, the SFDR of the synthesized sinusoid is 84.15 dBc. A ROM compression ratio of 597.3:1 was also achieved. The performance of the DDFS is compared with previously presented DDFS techniques and the results show that the proposed design has advantages of high ROM compression ratio and low hardware complexity.",
keywords = "DDS, Direct digital frequency synthesizer, Phase to sine amplitude conversion, Piecewise linear approximation",
author = "Omran, {Q. K.} and Islam, {Mohammad Tariqul} and Norbahiah Misran",
year = "2013",
doi = "10.5755/j01.eee.19.10.5905",
language = "English",
volume = "19",
pages = "103--108",
journal = "Elektronika ir Elektrotechnika",
issn = "1392-1215",
publisher = "Kauno Technologijos Universitetas",
number = "10",

}

TY - JOUR

T1 - FPGA-based implementation of a new phaseto-sine amplitude conversion architecture

AU - Omran, Q. K.

AU - Islam, Mohammad Tariqul

AU - Misran, Norbahiah

PY - 2013

Y1 - 2013

N2 - The classical structure of linear interpolationbased phase-to-sine mapper (PSM) consists of at least two ROMs for polynomial coefficient storage. Other architectures may include extra ROM for storing residual errors. However, ROMs dissipate high power and occupy a significant amount of the die area. This study presents a new technique that eliminates the ROM by including the computation of segment initial coefficients in the hardware. Therefore, it becomes possible to trim down noticeable hardware resources. The proposed direct digital frequency synthesizer (DDFS) architecture has been encoded in VHDL and synthesized with Quartus II software. Post simulation results show that the proposed design is capable of achieving the theoretical spurious-free dynamic range (SFDR) upper bound when optimal polynomial coefficients are considered. For 32 piecewise linear segments, the SFDR of the synthesized sinusoid is 84.15 dBc. A ROM compression ratio of 597.3:1 was also achieved. The performance of the DDFS is compared with previously presented DDFS techniques and the results show that the proposed design has advantages of high ROM compression ratio and low hardware complexity.

AB - The classical structure of linear interpolationbased phase-to-sine mapper (PSM) consists of at least two ROMs for polynomial coefficient storage. Other architectures may include extra ROM for storing residual errors. However, ROMs dissipate high power and occupy a significant amount of the die area. This study presents a new technique that eliminates the ROM by including the computation of segment initial coefficients in the hardware. Therefore, it becomes possible to trim down noticeable hardware resources. The proposed direct digital frequency synthesizer (DDFS) architecture has been encoded in VHDL and synthesized with Quartus II software. Post simulation results show that the proposed design is capable of achieving the theoretical spurious-free dynamic range (SFDR) upper bound when optimal polynomial coefficients are considered. For 32 piecewise linear segments, the SFDR of the synthesized sinusoid is 84.15 dBc. A ROM compression ratio of 597.3:1 was also achieved. The performance of the DDFS is compared with previously presented DDFS techniques and the results show that the proposed design has advantages of high ROM compression ratio and low hardware complexity.

KW - DDS

KW - Direct digital frequency synthesizer

KW - Phase to sine amplitude conversion

KW - Piecewise linear approximation

UR - http://www.scopus.com/inward/record.url?scp=84890737626&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84890737626&partnerID=8YFLogxK

U2 - 10.5755/j01.eee.19.10.5905

DO - 10.5755/j01.eee.19.10.5905

M3 - Article

AN - SCOPUS:84890737626

VL - 19

SP - 103

EP - 108

JO - Elektronika ir Elektrotechnika

JF - Elektronika ir Elektrotechnika

SN - 1392-1215

IS - 10

ER -