Encryption in TECB Mode

Modeling, Simulation and Synthesis

Md. Mamun Ibne Reaz, M. I. Ibrahimy, F. Mohd-Yasin, C. S. Wei, M. Kamada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard (DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25%) and a higher maximum operating frequency of 78.59 MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software counterpart.

Original languageEnglish
Title of host publicationCommunications in Computer and Information Science
Pages205-215
Number of pages11
Volume5
DOIs
Publication statusPublished - 2007
Externally publishedYes
EventAsia Simulation Conference 2007, AsiaSim 2007 - Seoul
Duration: 10 Oct 200712 Oct 2007

Publication series

NameCommunications in Computer and Information Science
Volume5
ISSN (Print)18650929

Other

OtherAsia Simulation Conference 2007, AsiaSim 2007
CitySeoul
Period10/10/0712/10/07

Fingerprint

Cryptography
Computer simulation
Computer hardware description languages
Data privacy
Computer hardware
Field programmable gate arrays (FPGA)
Internet
Hardware
Costs

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Ibne Reaz, M. M., Ibrahimy, M. I., Mohd-Yasin, F., Wei, C. S., & Kamada, M. (2007). Encryption in TECB Mode: Modeling, Simulation and Synthesis. In Communications in Computer and Information Science (Vol. 5, pp. 205-215). (Communications in Computer and Information Science; Vol. 5). https://doi.org/10.1007/978-3-540-77600-0_23

Encryption in TECB Mode : Modeling, Simulation and Synthesis. / Ibne Reaz, Md. Mamun; Ibrahimy, M. I.; Mohd-Yasin, F.; Wei, C. S.; Kamada, M.

Communications in Computer and Information Science. Vol. 5 2007. p. 205-215 (Communications in Computer and Information Science; Vol. 5).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ibne Reaz, MM, Ibrahimy, MI, Mohd-Yasin, F, Wei, CS & Kamada, M 2007, Encryption in TECB Mode: Modeling, Simulation and Synthesis. in Communications in Computer and Information Science. vol. 5, Communications in Computer and Information Science, vol. 5, pp. 205-215, Asia Simulation Conference 2007, AsiaSim 2007, Seoul, 10/10/07. https://doi.org/10.1007/978-3-540-77600-0_23
Ibne Reaz MM, Ibrahimy MI, Mohd-Yasin F, Wei CS, Kamada M. Encryption in TECB Mode: Modeling, Simulation and Synthesis. In Communications in Computer and Information Science. Vol. 5. 2007. p. 205-215. (Communications in Computer and Information Science). https://doi.org/10.1007/978-3-540-77600-0_23
Ibne Reaz, Md. Mamun ; Ibrahimy, M. I. ; Mohd-Yasin, F. ; Wei, C. S. ; Kamada, M. / Encryption in TECB Mode : Modeling, Simulation and Synthesis. Communications in Computer and Information Science. Vol. 5 2007. pp. 205-215 (Communications in Computer and Information Science).
@inproceedings{a1116f1a61fe4ee4ba3c0210c217db0d,
title = "Encryption in TECB Mode: Modeling, Simulation and Synthesis",
abstract = "The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard (DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25{\%}) and a higher maximum operating frequency of 78.59 MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software counterpart.",
author = "{Ibne Reaz}, {Md. Mamun} and Ibrahimy, {M. I.} and F. Mohd-Yasin and Wei, {C. S.} and M. Kamada",
year = "2007",
doi = "10.1007/978-3-540-77600-0_23",
language = "English",
isbn = "9783540775997",
volume = "5",
series = "Communications in Computer and Information Science",
pages = "205--215",
booktitle = "Communications in Computer and Information Science",

}

TY - GEN

T1 - Encryption in TECB Mode

T2 - Modeling, Simulation and Synthesis

AU - Ibne Reaz, Md. Mamun

AU - Ibrahimy, M. I.

AU - Mohd-Yasin, F.

AU - Wei, C. S.

AU - Kamada, M.

PY - 2007

Y1 - 2007

N2 - The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard (DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25%) and a higher maximum operating frequency of 78.59 MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software counterpart.

AB - The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard (DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25%) and a higher maximum operating frequency of 78.59 MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software counterpart.

UR - http://www.scopus.com/inward/record.url?scp=84885008435&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84885008435&partnerID=8YFLogxK

U2 - 10.1007/978-3-540-77600-0_23

DO - 10.1007/978-3-540-77600-0_23

M3 - Conference contribution

SN - 9783540775997

VL - 5

T3 - Communications in Computer and Information Science

SP - 205

EP - 215

BT - Communications in Computer and Information Science

ER -