Effects of gate stack structural and process defectivity on high- k dielectric dependence of nbti reliability in 32 nm technology node PMOSFETs

H. Hussin, N. Soin, Muhammad Faiz Bukhori, S. Wan Muhamad Hatta, Y. Abdul Wahab

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E ′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high- k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2are increased but is reduced by 11% when the SiO2interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

Original languageEnglish
Article number490829
JournalScientific World Journal
Volume2014
DOIs
Publication statusPublished - 2014

Fingerprint

Technology
Degradation
degradation
Temperature
trapping
temperature
Electric potential
hafnium
Hole traps
Threshold voltage
Silicon Dioxide
silicon
defect
stack
effect
High-k dielectric
oxide
Defects
simulation
Negative bias temperature instability

ASJC Scopus subject areas

  • Biochemistry, Genetics and Molecular Biology(all)
  • Environmental Science(all)
  • Medicine(all)

Cite this

Effects of gate stack structural and process defectivity on high- k dielectric dependence of nbti reliability in 32 nm technology node PMOSFETs. / Hussin, H.; Soin, N.; Bukhori, Muhammad Faiz; Wan Muhamad Hatta, S.; Abdul Wahab, Y.

In: Scientific World Journal, Vol. 2014, 490829, 2014.

Research output: Contribution to journalArticle

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abstract = "We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E ′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high- k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5{\%} when the thicknesses of HfO2are increased but is reduced by 11{\%} when the SiO2interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.",
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AU - Abdul Wahab, Y.

PY - 2014

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N2 - We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E ′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high- k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2are increased but is reduced by 11% when the SiO2interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

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