Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

A. H Afifah Maheran, P. Susthitha Menon N V Visvanathan, S. Shaari, T. Kalaivani, I. Ahmad, Z. A Noor Faizah, P. R. Apte

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.

Original languageEnglish
Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages178-181
Number of pages4
ISBN (Print)9781479957606
DOIs
Publication statusPublished - 10 Oct 2014
Event11th IEEE International Conference on Semiconductor Electronics, ICSE 2014 - Kuala Lumpur
Duration: 27 Aug 201429 Aug 2014

Other

Other11th IEEE International Conference on Semiconductor Electronics, ICSE 2014
CityKuala Lumpur
Period27/8/1429/8/14

Fingerprint

Taguchi methods
Threshold voltage
Metals
Fabrication
Tungsten
Polysilicon
Titanium dioxide
Transistors
Permittivity
Specifications
titanium dioxide

Keywords

  • 22 nm PMOS
  • high-k/metal gate
  • scaling down
  • Taguchi Method

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Maheran, A. H. A., N V Visvanathan, P. S. M., Shaari, S., Kalaivani, T., Ahmad, I., Faizah, Z. A. N., & Apte, P. R. (2014). Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 178-181). [6920825] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMELEC.2014.6920825

Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method. / Maheran, A. H Afifah; N V Visvanathan, P. Susthitha Menon; Shaari, S.; Kalaivani, T.; Ahmad, I.; Faizah, Z. A Noor; Apte, P. R.

IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. Institute of Electrical and Electronics Engineers Inc., 2014. p. 178-181 6920825.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Maheran, AHA, N V Visvanathan, PSM, Shaari, S, Kalaivani, T, Ahmad, I, Faizah, ZAN & Apte, PR 2014, Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 6920825, Institute of Electrical and Electronics Engineers Inc., pp. 178-181, 11th IEEE International Conference on Semiconductor Electronics, ICSE 2014, Kuala Lumpur, 27/8/14. https://doi.org/10.1109/SMELEC.2014.6920825
Maheran AHA, N V Visvanathan PSM, Shaari S, Kalaivani T, Ahmad I, Faizah ZAN et al. Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. Institute of Electrical and Electronics Engineers Inc. 2014. p. 178-181. 6920825 https://doi.org/10.1109/SMELEC.2014.6920825
Maheran, A. H Afifah ; N V Visvanathan, P. Susthitha Menon ; Shaari, S. ; Kalaivani, T. ; Ahmad, I. ; Faizah, Z. A Noor ; Apte, P. R. / Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 178-181
@inproceedings{20773773a96e43afa718e1c09b2c9431,
title = "Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method",
abstract = "This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7{\%} is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.",
keywords = "22 nm PMOS, high-k/metal gate, scaling down, Taguchi Method",
author = "Maheran, {A. H Afifah} and {N V Visvanathan}, {P. Susthitha Menon} and S. Shaari and T. Kalaivani and I. Ahmad and Faizah, {Z. A Noor} and Apte, {P. R.}",
year = "2014",
month = "10",
day = "10",
doi = "10.1109/SMELEC.2014.6920825",
language = "English",
isbn = "9781479957606",
pages = "178--181",
booktitle = "IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

AU - Maheran, A. H Afifah

AU - N V Visvanathan, P. Susthitha Menon

AU - Shaari, S.

AU - Kalaivani, T.

AU - Ahmad, I.

AU - Faizah, Z. A Noor

AU - Apte, P. R.

PY - 2014/10/10

Y1 - 2014/10/10

N2 - This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.

AB - This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.

KW - 22 nm PMOS

KW - high-k/metal gate

KW - scaling down

KW - Taguchi Method

UR - http://www.scopus.com/inward/record.url?scp=84908224581&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84908224581&partnerID=8YFLogxK

U2 - 10.1109/SMELEC.2014.6920825

DO - 10.1109/SMELEC.2014.6920825

M3 - Conference contribution

SN - 9781479957606

SP - 178

EP - 181

BT - IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

PB - Institute of Electrical and Electronics Engineers Inc.

ER -