Direct digital frequency synthesizer simulation and design by means of quartus-ModelSim

A. A. Alsharef, M. A. Mohd Ali, Hilmi Sanusi

Research output: Contribution to journalArticle

Abstract

A new full simulation, design and verification of a Direct Digital Frequency Synthesizer (DDFS), utilizing only one quarter of a given sinusoidal wave, are presented in this study. A reduction in the size of the LUT is accomplished as the new design requires storing only a quarter of the sine wave. The Register Transfer Level (RTL) and the Gate level is implemented by the Quartus II. The Quartus II will then invoke the ModelSim Altera software to simulate the output. The DDFS consists of three major models, mainly a Phase Accumulator (PA), a Phase Register and a Look Up Table (LUT). All of the mentioned models are realized by a Verilog code. The spurious free dynamic range is achieved with a value of -73 dB using a 16 bit phase accumulator. The proposed design is verified through the application of different input frequencies and obtained results showed that output frequency is directly proportional to the tuning input frequency.

Original languageEnglish
Pages (from-to)2172-2177
Number of pages6
JournalJournal of Applied Sciences
Volume12
Issue number20
DOIs
Publication statusPublished - 2012

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Frequency synthesizers
Computer hardware description languages
Tuning

Keywords

  • Digital phase locked loop
  • Direct digital synthesis
  • Field programmable gate array
  • Read only memoiy lockup table

ASJC Scopus subject areas

  • General

Cite this

Direct digital frequency synthesizer simulation and design by means of quartus-ModelSim. / Alsharef, A. A.; Mohd Ali, M. A.; Sanusi, Hilmi.

In: Journal of Applied Sciences, Vol. 12, No. 20, 2012, p. 2172-2177.

Research output: Contribution to journalArticle

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