Direct digital frequency synthesizer design and implementation on FPGA

A. A. Alsharef, M. A Mohd Ah, Hilmi Sanusi

Research output: Contribution to journalArticle

Abstract

This study presents a design and implementation of a direct digital frequency synthesizer based on Quarter Sine Wave. The RTL level simulation and gate level simulation of a proposed design is done by means of a Quartus-Model-Sim. This design is a digital part. The digital part consists of a Phase Accumulator (PA) and a Look up Table (LUT). The Phase Accumulator is implemented by means of a register along with an adder and feedback loop. LUT is implemented using verilog code. The size of LUT is reducing by storing quarter of sine wave in the ROM. This design was tested with various tuning frequencies and the result shows that the output frequency is directly proportional to the tuning input frequency.

Original languageEnglish
Pages (from-to)387-390
Number of pages4
JournalResearch Journal of Applied Sciences
Volume7
Issue number8
DOIs
Publication statusPublished - 2012

Fingerprint

frequency synthesizers
Frequency synthesizers
Field programmable gate arrays (FPGA)
sine waves
accumulators
Tuning
tuning
adding circuits
Computer hardware description languages
ROM
Adders
registers
simulation
Feedback
output

Keywords

  • Feedback loop
  • Frequency
  • Gate level simulation
  • Input frequency
  • Verilog code

ASJC Scopus subject areas

  • General
  • Engineering(all)

Cite this

Direct digital frequency synthesizer design and implementation on FPGA. / Alsharef, A. A.; Ah, M. A Mohd; Sanusi, Hilmi.

In: Research Journal of Applied Sciences, Vol. 7, No. 8, 2012, p. 387-390.

Research output: Contribution to journalArticle

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