Design perspective of low power, high efficiency shift registers

Mohd Marufuzzaman, Z. H. Jalil, Md. Mamun Ibne Reaz, L. F. Rahman

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In low-power digital design, especially in shift registers, flip-flops (FF) plays a significant role. In shift registers, the power consumption of system clock is estimated to be half of the overall system power. Therefore, selecting the right FF is very important for designing an compact size and low power shift register. In this paper, a review of different FF designs that have been applied for different shift register (SIPO, PIPO, SISO and PISO) is presented. The connection between FFs parameters and shift registers is also discussed. FFs architecture is evaluated via its average power, delay and power delay product. Comparative study showed that FFs have great effect on the performance quality of shift registers.

Original languageEnglish
Pages (from-to)310-321
Number of pages12
JournalJournal of Theoretical and Applied Information Technology
Volume79
Issue number2
Publication statusPublished - 20 Sep 2015

Fingerprint

Shift registers
Flip
High Efficiency
Flip flop circuits
Power System
Power Consumption
Comparative Study
Design
Clocks
Electric power utilization

Keywords

  • CMOC
  • Double edge triggered FF
  • FF
  • Shift register
  • Single edge triggered FF

ASJC Scopus subject areas

  • Computer Science(all)
  • Theoretical Computer Science

Cite this

Design perspective of low power, high efficiency shift registers. / Marufuzzaman, Mohd; Jalil, Z. H.; Ibne Reaz, Md. Mamun; Rahman, L. F.

In: Journal of Theoretical and Applied Information Technology, Vol. 79, No. 2, 20.09.2015, p. 310-321.

Research output: Contribution to journalArticle

@article{df220ed0a1d64807bbf330f79d8296c5,
title = "Design perspective of low power, high efficiency shift registers",
abstract = "In low-power digital design, especially in shift registers, flip-flops (FF) plays a significant role. In shift registers, the power consumption of system clock is estimated to be half of the overall system power. Therefore, selecting the right FF is very important for designing an compact size and low power shift register. In this paper, a review of different FF designs that have been applied for different shift register (SIPO, PIPO, SISO and PISO) is presented. The connection between FFs parameters and shift registers is also discussed. FFs architecture is evaluated via its average power, delay and power delay product. Comparative study showed that FFs have great effect on the performance quality of shift registers.",
keywords = "CMOC, Double edge triggered FF, FF, Shift register, Single edge triggered FF",
author = "Mohd Marufuzzaman and Jalil, {Z. H.} and {Ibne Reaz}, {Md. Mamun} and Rahman, {L. F.}",
year = "2015",
month = "9",
day = "20",
language = "English",
volume = "79",
pages = "310--321",
journal = "Journal of Theoretical and Applied Information Technology",
issn = "1992-8645",
publisher = "Asian Research Publishing Network (ARPN)",
number = "2",

}

TY - JOUR

T1 - Design perspective of low power, high efficiency shift registers

AU - Marufuzzaman, Mohd

AU - Jalil, Z. H.

AU - Ibne Reaz, Md. Mamun

AU - Rahman, L. F.

PY - 2015/9/20

Y1 - 2015/9/20

N2 - In low-power digital design, especially in shift registers, flip-flops (FF) plays a significant role. In shift registers, the power consumption of system clock is estimated to be half of the overall system power. Therefore, selecting the right FF is very important for designing an compact size and low power shift register. In this paper, a review of different FF designs that have been applied for different shift register (SIPO, PIPO, SISO and PISO) is presented. The connection between FFs parameters and shift registers is also discussed. FFs architecture is evaluated via its average power, delay and power delay product. Comparative study showed that FFs have great effect on the performance quality of shift registers.

AB - In low-power digital design, especially in shift registers, flip-flops (FF) plays a significant role. In shift registers, the power consumption of system clock is estimated to be half of the overall system power. Therefore, selecting the right FF is very important for designing an compact size and low power shift register. In this paper, a review of different FF designs that have been applied for different shift register (SIPO, PIPO, SISO and PISO) is presented. The connection between FFs parameters and shift registers is also discussed. FFs architecture is evaluated via its average power, delay and power delay product. Comparative study showed that FFs have great effect on the performance quality of shift registers.

KW - CMOC

KW - Double edge triggered FF

KW - FF

KW - Shift register

KW - Single edge triggered FF

UR - http://www.scopus.com/inward/record.url?scp=84942104419&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84942104419&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:84942104419

VL - 79

SP - 310

EP - 321

JO - Journal of Theoretical and Applied Information Technology

JF - Journal of Theoretical and Applied Information Technology

SN - 1992-8645

IS - 2

ER -