Design of low power phase detector in 0.13 um CMOS

F. Labonnah Rahman, Md. Mamun Ibne Reaz, Mohammad Marufuzzman, A. Nadzron Hamid

Research output: Contribution to journalArticle

Abstract

This paper presents a designed of Phase Detector (PD) which applied into the Phase Locked Loop (PLL) circuits which commonly used in the system of communication. Currently, the design and development of low power PD are always crucial concerned by circuits designer to minimize the power consuming. The primary goal of this work is to design a low power PD. The architectures of PD also reduce the complexity structure of the circuit. To varying the low power, the resistor in the circuits was replaced and utilized with PMOS and current bias with NMOS transistor. Providing power supply 1.8V, the PD dissipated to 20.9 mW of its power. This proposed PD was designed in Mentor Graphics environment by using 0.13-μm CMOS process technology, TSMC.

Original languageEnglish
Pages (from-to)59-62
Number of pages4
JournalJournal of Electrical and Electronics Engineering
Volume10
Issue number1
Publication statusPublished - 1 May 2017

Fingerprint

Detectors
Networks (circuits)
Bias currents
Phase locked loops
Resistors
Transistors
Communication

Keywords

  • CMOS
  • PD
  • PLL
  • Power

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Design of low power phase detector in 0.13 um CMOS. / Rahman, F. Labonnah; Ibne Reaz, Md. Mamun; Marufuzzman, Mohammad; Hamid, A. Nadzron.

In: Journal of Electrical and Electronics Engineering, Vol. 10, No. 1, 01.05.2017, p. 59-62.

Research output: Contribution to journalArticle

Rahman, FL, Ibne Reaz, MM, Marufuzzman, M & Hamid, AN 2017, 'Design of low power phase detector in 0.13 um CMOS', Journal of Electrical and Electronics Engineering, vol. 10, no. 1, pp. 59-62.
Rahman, F. Labonnah ; Ibne Reaz, Md. Mamun ; Marufuzzman, Mohammad ; Hamid, A. Nadzron. / Design of low power phase detector in 0.13 um CMOS. In: Journal of Electrical and Electronics Engineering. 2017 ; Vol. 10, No. 1. pp. 59-62.
@article{a7643cf1dc5d45f393011c20e38033ab,
title = "Design of low power phase detector in 0.13 um CMOS",
abstract = "This paper presents a designed of Phase Detector (PD) which applied into the Phase Locked Loop (PLL) circuits which commonly used in the system of communication. Currently, the design and development of low power PD are always crucial concerned by circuits designer to minimize the power consuming. The primary goal of this work is to design a low power PD. The architectures of PD also reduce the complexity structure of the circuit. To varying the low power, the resistor in the circuits was replaced and utilized with PMOS and current bias with NMOS transistor. Providing power supply 1.8V, the PD dissipated to 20.9 mW of its power. This proposed PD was designed in Mentor Graphics environment by using 0.13-μm CMOS process technology, TSMC.",
keywords = "CMOS, PD, PLL, Power",
author = "Rahman, {F. Labonnah} and {Ibne Reaz}, {Md. Mamun} and Mohammad Marufuzzman and Hamid, {A. Nadzron}",
year = "2017",
month = "5",
day = "1",
language = "English",
volume = "10",
pages = "59--62",
journal = "Journal of Electrical and Electronics Engineering",
issn = "1844-6035",
publisher = "Editura Universitati din Oradea",
number = "1",

}

TY - JOUR

T1 - Design of low power phase detector in 0.13 um CMOS

AU - Rahman, F. Labonnah

AU - Ibne Reaz, Md. Mamun

AU - Marufuzzman, Mohammad

AU - Hamid, A. Nadzron

PY - 2017/5/1

Y1 - 2017/5/1

N2 - This paper presents a designed of Phase Detector (PD) which applied into the Phase Locked Loop (PLL) circuits which commonly used in the system of communication. Currently, the design and development of low power PD are always crucial concerned by circuits designer to minimize the power consuming. The primary goal of this work is to design a low power PD. The architectures of PD also reduce the complexity structure of the circuit. To varying the low power, the resistor in the circuits was replaced and utilized with PMOS and current bias with NMOS transistor. Providing power supply 1.8V, the PD dissipated to 20.9 mW of its power. This proposed PD was designed in Mentor Graphics environment by using 0.13-μm CMOS process technology, TSMC.

AB - This paper presents a designed of Phase Detector (PD) which applied into the Phase Locked Loop (PLL) circuits which commonly used in the system of communication. Currently, the design and development of low power PD are always crucial concerned by circuits designer to minimize the power consuming. The primary goal of this work is to design a low power PD. The architectures of PD also reduce the complexity structure of the circuit. To varying the low power, the resistor in the circuits was replaced and utilized with PMOS and current bias with NMOS transistor. Providing power supply 1.8V, the PD dissipated to 20.9 mW of its power. This proposed PD was designed in Mentor Graphics environment by using 0.13-μm CMOS process technology, TSMC.

KW - CMOS

KW - PD

KW - PLL

KW - Power

UR - http://www.scopus.com/inward/record.url?scp=85026651350&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85026651350&partnerID=8YFLogxK

M3 - Article

VL - 10

SP - 59

EP - 62

JO - Journal of Electrical and Electronics Engineering

JF - Journal of Electrical and Electronics Engineering

SN - 1844-6035

IS - 1

ER -