Design of high speed and low offset dynamic latch comparator in 0.18 μm CMOS process

Labonnah Farzana Rahman, Md. Mamun Ibne Reaz, Chia Chieu Yin, Mohammad Alauddin Mohammad Ali, Mohammad Marufuzzaman

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 mm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 mW from 1.8 V supply and 88.05 mA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.

Original languageEnglish
Article numbere108634
JournalPLoS One
Volume9
Issue number10
DOIs
Publication statusPublished - 9 Oct 2014

Fingerprint

Technology
energy efficiency
Research
Integrated circuit layout
Coupled circuits
Flip flop circuits
Energy efficiency
Networks (circuits)
Electric potential

ASJC Scopus subject areas

  • Agricultural and Biological Sciences(all)
  • Biochemistry, Genetics and Molecular Biology(all)
  • Medicine(all)

Cite this

Design of high speed and low offset dynamic latch comparator in 0.18 μm CMOS process. / Rahman, Labonnah Farzana; Ibne Reaz, Md. Mamun; Yin, Chia Chieu; Ali, Mohammad Alauddin Mohammad; Marufuzzaman, Mohammad.

In: PLoS One, Vol. 9, No. 10, e108634, 09.10.2014.

Research output: Contribution to journalArticle

Rahman, Labonnah Farzana ; Ibne Reaz, Md. Mamun ; Yin, Chia Chieu ; Ali, Mohammad Alauddin Mohammad ; Marufuzzaman, Mohammad. / Design of high speed and low offset dynamic latch comparator in 0.18 μm CMOS process. In: PLoS One. 2014 ; Vol. 9, No. 10.
@article{c6cf88f53196486ba48dabd678d13a35,
title = "Design of high speed and low offset dynamic latch comparator in 0.18 μm CMOS process",
abstract = "The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 mm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 mW from 1.8 V supply and 88.05 mA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.",
author = "Rahman, {Labonnah Farzana} and {Ibne Reaz}, {Md. Mamun} and Yin, {Chia Chieu} and Ali, {Mohammad Alauddin Mohammad} and Mohammad Marufuzzaman",
year = "2014",
month = "10",
day = "9",
doi = "10.1371/journal.pone.0108634",
language = "English",
volume = "9",
journal = "PLoS One",
issn = "1932-6203",
publisher = "Public Library of Science",
number = "10",

}

TY - JOUR

T1 - Design of high speed and low offset dynamic latch comparator in 0.18 μm CMOS process

AU - Rahman, Labonnah Farzana

AU - Ibne Reaz, Md. Mamun

AU - Yin, Chia Chieu

AU - Ali, Mohammad Alauddin Mohammad

AU - Marufuzzaman, Mohammad

PY - 2014/10/9

Y1 - 2014/10/9

N2 - The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 mm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 mW from 1.8 V supply and 88.05 mA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.

AB - The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 mm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 mW from 1.8 V supply and 88.05 mA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.

UR - http://www.scopus.com/inward/record.url?scp=84907833270&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84907833270&partnerID=8YFLogxK

U2 - 10.1371/journal.pone.0108634

DO - 10.1371/journal.pone.0108634

M3 - Article

C2 - 25299266

AN - SCOPUS:84907833270

VL - 9

JO - PLoS One

JF - PLoS One

SN - 1932-6203

IS - 10

M1 - e108634

ER -