Design of a micro-UART for SoC application

Liakot Ali, Roslina Sidek, Ishak Aris, Alauddin Mohd. Ali, Bambang Sunaryo Suparjo

    Research output: Contribution to journalArticle

    17 Citations (Scopus)

    Abstract

    This paper presents the design of a universal asynchronous receiver and transmitter (UART), which is fully functional and synthesizeable. Due to its modularity, configurability and extremely compact size, the proposed UART is named as micro-UART and it is ideal for system-on-a-chip (SoC) application. The core is usable as an intellectual property. Verilog hardware description language (HDL) in the Altera's MAX-PLUS II environment has been used for its design, compilation and simulation. The UART has been implemented using Altera's FPGA technology.

    Original languageEnglish
    Pages (from-to)257-268
    Number of pages12
    JournalComputers and Electrical Engineering
    Volume30
    Issue number4
    DOIs
    Publication statusPublished - Jun 2004

    Fingerprint

    Transmitters
    Computer hardware description languages
    Intellectual property
    Field programmable gate arrays (FPGA)

    Keywords

    • FPGA
    • HDL
    • Serial communication
    • SoC
    • UART

    ASJC Scopus subject areas

    • Control and Systems Engineering
    • Electrical and Electronic Engineering

    Cite this

    Ali, L., Sidek, R., Aris, I., Mohd. Ali, A., & Suparjo, B. S. (2004). Design of a micro-UART for SoC application. Computers and Electrical Engineering, 30(4), 257-268. https://doi.org/10.1016/j.compeleceng.2003.01.002

    Design of a micro-UART for SoC application. / Ali, Liakot; Sidek, Roslina; Aris, Ishak; Mohd. Ali, Alauddin; Suparjo, Bambang Sunaryo.

    In: Computers and Electrical Engineering, Vol. 30, No. 4, 06.2004, p. 257-268.

    Research output: Contribution to journalArticle

    Ali, L, Sidek, R, Aris, I, Mohd. Ali, A & Suparjo, BS 2004, 'Design of a micro-UART for SoC application', Computers and Electrical Engineering, vol. 30, no. 4, pp. 257-268. https://doi.org/10.1016/j.compeleceng.2003.01.002
    Ali, Liakot ; Sidek, Roslina ; Aris, Ishak ; Mohd. Ali, Alauddin ; Suparjo, Bambang Sunaryo. / Design of a micro-UART for SoC application. In: Computers and Electrical Engineering. 2004 ; Vol. 30, No. 4. pp. 257-268.
    @article{f65122f5e52f4bb08d2a81a9c898d865,
    title = "Design of a micro-UART for SoC application",
    abstract = "This paper presents the design of a universal asynchronous receiver and transmitter (UART), which is fully functional and synthesizeable. Due to its modularity, configurability and extremely compact size, the proposed UART is named as micro-UART and it is ideal for system-on-a-chip (SoC) application. The core is usable as an intellectual property. Verilog hardware description language (HDL) in the Altera's MAX-PLUS II environment has been used for its design, compilation and simulation. The UART has been implemented using Altera's FPGA technology.",
    keywords = "FPGA, HDL, Serial communication, SoC, UART",
    author = "Liakot Ali and Roslina Sidek and Ishak Aris and {Mohd. Ali}, Alauddin and Suparjo, {Bambang Sunaryo}",
    year = "2004",
    month = "6",
    doi = "10.1016/j.compeleceng.2003.01.002",
    language = "English",
    volume = "30",
    pages = "257--268",
    journal = "Computers and Electrical Engineering",
    issn = "0045-7906",
    publisher = "Elsevier Limited",
    number = "4",

    }

    TY - JOUR

    T1 - Design of a micro-UART for SoC application

    AU - Ali, Liakot

    AU - Sidek, Roslina

    AU - Aris, Ishak

    AU - Mohd. Ali, Alauddin

    AU - Suparjo, Bambang Sunaryo

    PY - 2004/6

    Y1 - 2004/6

    N2 - This paper presents the design of a universal asynchronous receiver and transmitter (UART), which is fully functional and synthesizeable. Due to its modularity, configurability and extremely compact size, the proposed UART is named as micro-UART and it is ideal for system-on-a-chip (SoC) application. The core is usable as an intellectual property. Verilog hardware description language (HDL) in the Altera's MAX-PLUS II environment has been used for its design, compilation and simulation. The UART has been implemented using Altera's FPGA technology.

    AB - This paper presents the design of a universal asynchronous receiver and transmitter (UART), which is fully functional and synthesizeable. Due to its modularity, configurability and extremely compact size, the proposed UART is named as micro-UART and it is ideal for system-on-a-chip (SoC) application. The core is usable as an intellectual property. Verilog hardware description language (HDL) in the Altera's MAX-PLUS II environment has been used for its design, compilation and simulation. The UART has been implemented using Altera's FPGA technology.

    KW - FPGA

    KW - HDL

    KW - Serial communication

    KW - SoC

    KW - UART

    UR - http://www.scopus.com/inward/record.url?scp=4444237493&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=4444237493&partnerID=8YFLogxK

    U2 - 10.1016/j.compeleceng.2003.01.002

    DO - 10.1016/j.compeleceng.2003.01.002

    M3 - Article

    AN - SCOPUS:4444237493

    VL - 30

    SP - 257

    EP - 268

    JO - Computers and Electrical Engineering

    JF - Computers and Electrical Engineering

    SN - 0045-7906

    IS - 4

    ER -