Design of a low power static frequency divider

Tan Chen Hou, Noorfazila Kamal, Khairuddin Jaafar, Md. Mamun Ibne Reaz, Jahariah Sampe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Frequency divider is an important unit in phase-locked loop (PLL) which is widely used in RF frequency synthesizer. The divider circuit has been identified as the main contributor to PLL power dissipation. Therefore, frequency divider with low power dissipation is necessary. The objectives of this work are to design a frequency divider with low power dissipation which is able to operate under low supply voltage using Silterra 0.13μm CMOS technology. This work also compares performance of the proposed frequency divider to the conventional frequency divider, which is implemented in MOSFET. The proposed frequency divider is based on TSPC topology. DTMOS and FBB techniques have been adopted in the proposed frequency divider to enable it operate at low supply voltage, results in low power dissipation. The performance of the proposed frequency divider in term of maximum operating frequency, supply voltage, power dissipation and phase noise have been compared to those of conventional frequency divider which is implemented using MOSFET. The result of this work has shown that the proposed DTMOS-FBB frequency divider is able to operate up to 2.5GHz from 0.6V supply voltage. It only dissipates 29μW of power. Compared to the MOSFET frequency divider, at the same operating frequency it dissipates 61 μW from 1.2V supply voltage. It is shown the proposed DTMOS-FBB frequency divider has reduced up to 52% of power dissipation when compared to MOSFET frequency divider.

Original languageEnglish
Title of host publication2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages199-202
Number of pages4
ISBN (Electronic)9781509028894
DOIs
Publication statusPublished - 27 Mar 2017
Event2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 - Putrajaya, Malaysia
Duration: 14 Nov 201616 Nov 2016

Other

Other2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
CountryMalaysia
CityPutrajaya
Period14/11/1616/11/16

Fingerprint

frequency dividers
Energy dissipation
Electric potential
dissipation
Phase locked loops
field effect transistors
electric potential
Frequency synthesizers
Phase noise
Topology
frequency synthesizers
Networks (circuits)
dividers

Keywords

  • DTMOS
  • Forward-body biasing
  • Frequency divider
  • True-single-phase-clock

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Biomedical Engineering
  • Control and Systems Engineering
  • Hardware and Architecture
  • Computer Networks and Communications
  • Instrumentation

Cite this

Hou, T. C., Kamal, N., Jaafar, K., Ibne Reaz, M. M., & Sampe, J. (2017). Design of a low power static frequency divider. In 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 (pp. 199-202). [7888038] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICAEES.2016.7888038

Design of a low power static frequency divider. / Hou, Tan Chen; Kamal, Noorfazila; Jaafar, Khairuddin; Ibne Reaz, Md. Mamun; Sampe, Jahariah.

2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 199-202 7888038.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hou, TC, Kamal, N, Jaafar, K, Ibne Reaz, MM & Sampe, J 2017, Design of a low power static frequency divider. in 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016., 7888038, Institute of Electrical and Electronics Engineers Inc., pp. 199-202, 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016, Putrajaya, Malaysia, 14/11/16. https://doi.org/10.1109/ICAEES.2016.7888038
Hou TC, Kamal N, Jaafar K, Ibne Reaz MM, Sampe J. Design of a low power static frequency divider. In 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 199-202. 7888038 https://doi.org/10.1109/ICAEES.2016.7888038
Hou, Tan Chen ; Kamal, Noorfazila ; Jaafar, Khairuddin ; Ibne Reaz, Md. Mamun ; Sampe, Jahariah. / Design of a low power static frequency divider. 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 199-202
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N2 - Frequency divider is an important unit in phase-locked loop (PLL) which is widely used in RF frequency synthesizer. The divider circuit has been identified as the main contributor to PLL power dissipation. Therefore, frequency divider with low power dissipation is necessary. The objectives of this work are to design a frequency divider with low power dissipation which is able to operate under low supply voltage using Silterra 0.13μm CMOS technology. This work also compares performance of the proposed frequency divider to the conventional frequency divider, which is implemented in MOSFET. The proposed frequency divider is based on TSPC topology. DTMOS and FBB techniques have been adopted in the proposed frequency divider to enable it operate at low supply voltage, results in low power dissipation. The performance of the proposed frequency divider in term of maximum operating frequency, supply voltage, power dissipation and phase noise have been compared to those of conventional frequency divider which is implemented using MOSFET. The result of this work has shown that the proposed DTMOS-FBB frequency divider is able to operate up to 2.5GHz from 0.6V supply voltage. It only dissipates 29μW of power. Compared to the MOSFET frequency divider, at the same operating frequency it dissipates 61 μW from 1.2V supply voltage. It is shown the proposed DTMOS-FBB frequency divider has reduced up to 52% of power dissipation when compared to MOSFET frequency divider.

AB - Frequency divider is an important unit in phase-locked loop (PLL) which is widely used in RF frequency synthesizer. The divider circuit has been identified as the main contributor to PLL power dissipation. Therefore, frequency divider with low power dissipation is necessary. The objectives of this work are to design a frequency divider with low power dissipation which is able to operate under low supply voltage using Silterra 0.13μm CMOS technology. This work also compares performance of the proposed frequency divider to the conventional frequency divider, which is implemented in MOSFET. The proposed frequency divider is based on TSPC topology. DTMOS and FBB techniques have been adopted in the proposed frequency divider to enable it operate at low supply voltage, results in low power dissipation. The performance of the proposed frequency divider in term of maximum operating frequency, supply voltage, power dissipation and phase noise have been compared to those of conventional frequency divider which is implemented using MOSFET. The result of this work has shown that the proposed DTMOS-FBB frequency divider is able to operate up to 2.5GHz from 0.6V supply voltage. It only dissipates 29μW of power. Compared to the MOSFET frequency divider, at the same operating frequency it dissipates 61 μW from 1.2V supply voltage. It is shown the proposed DTMOS-FBB frequency divider has reduced up to 52% of power dissipation when compared to MOSFET frequency divider.

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