Design of a low power dissipation and low input voltage range level shifter in Cedec 0.18-μm Cmos process

Norfazliana Binti Romli, Md. Mamun Ibne Reaz, Mohammad Arif Sobhan Bhuiyan, Hafizah Husain

Research output: Contribution to journalArticle

19 Citations (Scopus)

Abstract

Level shifter (LS) circuits are widely used as an interface for multiple voltage domains in modern ICs and System on Chips (SoCs). Low power dissipation is one of the main design considerations for high performance level shifters. This paper presents the design and performance of a low power dissipation and low input voltage range level shifter in CEDEC 0.18-μm CMOS process. Simulation results shows that the level shifter is able to perform voltage level shifting from low voltage level of 0.4 - 0.7 V into high voltage level of 3 V. The obtained power dissipation is only 1.49 nW for 0.4 V and 1-kHz input pulse. This level shifter fulfills the needs of lower power systems and will be very useful for ICs and SoCs.

Original languageEnglish
Pages (from-to)1140-1148
Number of pages9
JournalWorld Applied Sciences Journal
Volume19
Issue number8
DOIs
Publication statusPublished - 2012

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Energy dissipation
Electric potential
Networks (circuits)
System-on-chip

Keywords

  • CMOS
  • IC
  • Level shifter
  • Low loss
  • Output driver
  • SOC

ASJC Scopus subject areas

  • General

Cite this

Design of a low power dissipation and low input voltage range level shifter in Cedec 0.18-μm Cmos process. / Romli, Norfazliana Binti; Ibne Reaz, Md. Mamun; Bhuiyan, Mohammad Arif Sobhan; Husain, Hafizah.

In: World Applied Sciences Journal, Vol. 19, No. 8, 2012, p. 1140-1148.

Research output: Contribution to journalArticle

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