Design of a low-power CMOS Level Shifter for low-delay SoCs in silterra 0.13 μm CMOS process

Mohammad Torikul Islam Badal, Md. Mamun Ibne Reaz, Araf Farayez, Siti A.B. Ramli, Noorfazila Kamal

Research output: Contribution to journalArticle

Abstract

Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 μm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 μm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.

Original languageEnglish
Pages (from-to)10-15
Number of pages6
JournalJournal of Engineering Science and Technology Review
Volume10
Issue number4
DOIs
Publication statusPublished - 2017

Fingerprint

Energy dissipation
Networks (circuits)
Electric potential
Electric power utilization
System-on-chip

Keywords

  • CMOS
  • Delay
  • Level Shifter
  • Multi-supply voltage design
  • SoC
  • Ultra-Low Power

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Design of a low-power CMOS Level Shifter for low-delay SoCs in silterra 0.13 μm CMOS process. / Badal, Mohammad Torikul Islam; Ibne Reaz, Md. Mamun; Farayez, Araf; Ramli, Siti A.B.; Kamal, Noorfazila.

In: Journal of Engineering Science and Technology Review, Vol. 10, No. 4, 2017, p. 10-15.

Research output: Contribution to journalArticle

@article{4655ba139891410480d221b3c6c3404b,
title = "Design of a low-power CMOS Level Shifter for low-delay SoCs in silterra 0.13 μm CMOS process",
abstract = "Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 μm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 μm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.",
keywords = "CMOS, Delay, Level Shifter, Multi-supply voltage design, SoC, Ultra-Low Power",
author = "Badal, {Mohammad Torikul Islam} and {Ibne Reaz}, {Md. Mamun} and Araf Farayez and Ramli, {Siti A.B.} and Noorfazila Kamal",
year = "2017",
doi = "10.25103/jestr.104.02",
language = "English",
volume = "10",
pages = "10--15",
journal = "Journal of Engineering Science and Technology Review",
issn = "1791-9320",
publisher = "Kavala Institute of Technology",
number = "4",

}

TY - JOUR

T1 - Design of a low-power CMOS Level Shifter for low-delay SoCs in silterra 0.13 μm CMOS process

AU - Badal, Mohammad Torikul Islam

AU - Ibne Reaz, Md. Mamun

AU - Farayez, Araf

AU - Ramli, Siti A.B.

AU - Kamal, Noorfazila

PY - 2017

Y1 - 2017

N2 - Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 μm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 μm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.

AB - Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 μm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 μm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.

KW - CMOS

KW - Delay

KW - Level Shifter

KW - Multi-supply voltage design

KW - SoC

KW - Ultra-Low Power

UR - http://www.scopus.com/inward/record.url?scp=85030028921&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85030028921&partnerID=8YFLogxK

U2 - 10.25103/jestr.104.02

DO - 10.25103/jestr.104.02

M3 - Article

AN - SCOPUS:85030028921

VL - 10

SP - 10

EP - 15

JO - Journal of Engineering Science and Technology Review

JF - Journal of Engineering Science and Technology Review

SN - 1791-9320

IS - 4

ER -