Design of a low power and wide band true single-phase clock frequency divider

Mohd Azfar Bin Tajul Arifin, Md. Mamun Ibne Reaz, Mohammad Arif Sobhan Bhuiyan, Hafizah Husain

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

The design of frequency synthesizer, often implemented by a phase-locked loop (PLL), is a challenging task for RF designers in terms of power dissipation. In this paper an ultra-low power wide band 2/3 prescaler simulated by CEDEC 0.18 μm CMOS technology is presented. The proposed prescaler is capable of operating up to 8 GHz with smooth output waveform for divide-by-2 operation. Compared with concurrent extended true single phase clock (E-TSPC) circuits at supply voltage of 1.8 V, more than 50% reduction in total power consumption is achieved for both divide-by-2 and divideby- 3 operations. It consumes 0.05 mW and 0.68 mW of power during divide-by-2 and divide-by-3 modes respectively.

Original languageEnglish
Pages (from-to)73-79
Number of pages7
JournalAustralian Journal of Basic and Applied Sciences
Volume6
Issue number7
Publication statusPublished - Jul 2012

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Frequency synthesizers
Phase locked loops
Clocks
Energy dissipation
Electric power utilization
Networks (circuits)
Electric potential

Keywords

  • E-TSPC
  • Frequency divider
  • Prescaler
  • True single-phase clock (TSPC)

ASJC Scopus subject areas

  • General

Cite this

Design of a low power and wide band true single-phase clock frequency divider. / Arifin, Mohd Azfar Bin Tajul; Ibne Reaz, Md. Mamun; Bhuiyan, Mohammad Arif Sobhan; Husain, Hafizah.

In: Australian Journal of Basic and Applied Sciences, Vol. 6, No. 7, 07.2012, p. 73-79.

Research output: Contribution to journalArticle

Arifin, Mohd Azfar Bin Tajul ; Ibne Reaz, Md. Mamun ; Bhuiyan, Mohammad Arif Sobhan ; Husain, Hafizah. / Design of a low power and wide band true single-phase clock frequency divider. In: Australian Journal of Basic and Applied Sciences. 2012 ; Vol. 6, No. 7. pp. 73-79.
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