Design of a low-power and high throughput error detection and correction circuit using the 4T EX-OR method

Research output: Contribution to journalArticle

Abstract

This paper describes an efficient implementation of an error correction circuit based on single error detection and correction with check bit pre-computation. The core component of the proposed 4-bit EX-OR circuit was designed using the CMOS cascade method. This paper presents a 4-input EX-OR gate that was developed from a 2-input EX-OR gate using the bit slice method. The proposed architecture retains the modified Error Correction Code (ECC) circuit. The proposed 4-input EX-OR gate and its auxiliary components such as AND, MUX and D Flip-Flop were schematized using the DSCH tool and the layouts was analysed using the BSIM4 analyser. The simulation results were obtained and compared with the performance of existing circuits. LVS verification was performed on the modified ECC circuit at CMOS 70 nm feature size and its corresponding voltage of 0.7V. The modified ECC circuit simulation results were analysed and compared with the performance of existing circuits in terms of propagation delay, power dissipation, area, latency, and throughput. The proposed ECC circuit showed an improved performance with existing circuit low power dissipation (94.41%) and high throughput (95.20%).

Original languageEnglish
Pages (from-to)2010-2027
Number of pages18
JournalJournal of Engineering Science and Technology
Volume12
Issue number8
Publication statusPublished - 2017

Fingerprint

Error detection
Error correction
Throughput
Networks (circuits)
Energy dissipation
Flip flop circuits
Circuit simulation
Electric potential

Keywords

  • BSIM 4
  • ECC
  • EX-OR gate
  • MUX
  • Power dissipation
  • Propagation delay
  • Throughput

ASJC Scopus subject areas

  • Engineering(all)

Cite this

@article{3d2ffc990275413a87c732dc5f208ea9,
title = "Design of a low-power and high throughput error detection and correction circuit using the 4T EX-OR method",
abstract = "This paper describes an efficient implementation of an error correction circuit based on single error detection and correction with check bit pre-computation. The core component of the proposed 4-bit EX-OR circuit was designed using the CMOS cascade method. This paper presents a 4-input EX-OR gate that was developed from a 2-input EX-OR gate using the bit slice method. The proposed architecture retains the modified Error Correction Code (ECC) circuit. The proposed 4-input EX-OR gate and its auxiliary components such as AND, MUX and D Flip-Flop were schematized using the DSCH tool and the layouts was analysed using the BSIM4 analyser. The simulation results were obtained and compared with the performance of existing circuits. LVS verification was performed on the modified ECC circuit at CMOS 70 nm feature size and its corresponding voltage of 0.7V. The modified ECC circuit simulation results were analysed and compared with the performance of existing circuits in terms of propagation delay, power dissipation, area, latency, and throughput. The proposed ECC circuit showed an improved performance with existing circuit low power dissipation (94.41{\%}) and high throughput (95.20{\%}).",
keywords = "BSIM 4, ECC, EX-OR gate, MUX, Power dissipation, Propagation delay, Throughput",
author = "S. Kavitha and Hashim, {Fazida Hanim} and {Ibne Reaz}, {Md. Mamun} and Noorfazila Kamal",
year = "2017",
language = "English",
volume = "12",
pages = "2010--2027",
journal = "Journal of Engineering Science and Technology",
issn = "1823-4690",
publisher = "Taylor's University College",
number = "8",

}

TY - JOUR

T1 - Design of a low-power and high throughput error detection and correction circuit using the 4T EX-OR method

AU - Kavitha, S.

AU - Hashim, Fazida Hanim

AU - Ibne Reaz, Md. Mamun

AU - Kamal, Noorfazila

PY - 2017

Y1 - 2017

N2 - This paper describes an efficient implementation of an error correction circuit based on single error detection and correction with check bit pre-computation. The core component of the proposed 4-bit EX-OR circuit was designed using the CMOS cascade method. This paper presents a 4-input EX-OR gate that was developed from a 2-input EX-OR gate using the bit slice method. The proposed architecture retains the modified Error Correction Code (ECC) circuit. The proposed 4-input EX-OR gate and its auxiliary components such as AND, MUX and D Flip-Flop were schematized using the DSCH tool and the layouts was analysed using the BSIM4 analyser. The simulation results were obtained and compared with the performance of existing circuits. LVS verification was performed on the modified ECC circuit at CMOS 70 nm feature size and its corresponding voltage of 0.7V. The modified ECC circuit simulation results were analysed and compared with the performance of existing circuits in terms of propagation delay, power dissipation, area, latency, and throughput. The proposed ECC circuit showed an improved performance with existing circuit low power dissipation (94.41%) and high throughput (95.20%).

AB - This paper describes an efficient implementation of an error correction circuit based on single error detection and correction with check bit pre-computation. The core component of the proposed 4-bit EX-OR circuit was designed using the CMOS cascade method. This paper presents a 4-input EX-OR gate that was developed from a 2-input EX-OR gate using the bit slice method. The proposed architecture retains the modified Error Correction Code (ECC) circuit. The proposed 4-input EX-OR gate and its auxiliary components such as AND, MUX and D Flip-Flop were schematized using the DSCH tool and the layouts was analysed using the BSIM4 analyser. The simulation results were obtained and compared with the performance of existing circuits. LVS verification was performed on the modified ECC circuit at CMOS 70 nm feature size and its corresponding voltage of 0.7V. The modified ECC circuit simulation results were analysed and compared with the performance of existing circuits in terms of propagation delay, power dissipation, area, latency, and throughput. The proposed ECC circuit showed an improved performance with existing circuit low power dissipation (94.41%) and high throughput (95.20%).

KW - BSIM 4

KW - ECC

KW - EX-OR gate

KW - MUX

KW - Power dissipation

KW - Propagation delay

KW - Throughput

UR - http://www.scopus.com/inward/record.url?scp=85026896645&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85026896645&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:85026896645

VL - 12

SP - 2010

EP - 2027

JO - Journal of Engineering Science and Technology

JF - Journal of Engineering Science and Technology

SN - 1823-4690

IS - 8

ER -