Design of 4-bit memory column dram cell in 0.18 μim CMOS process

Nasima Sedaghati, Md. Mamun Ibne Reaz, Labonnah F. Rahman, Hafizah Husain

Research output: Contribution to journalArticle

Abstract

A Dynamic Random Access Memories (DRAM) memory cell is a capacitor that is charged to produce a 1 or a 0. Over the years, several different structures have been used to create the memoiy cells on a chip. In today's technologies, the capacitive storage element of the memoiy cell is used to create trenched filled with dielectric material. However to progress to the next generation DRAM, all the major physical limitations like circuit complexity, longer read/write times and delays of the 1-Transistor (1-T) and capacitor storage cell need to overcome. In this research, a 4-bit memory column cell for DRAM is presented. To design the column cell, 3-transistor DRAM is chosen as it is distinguished from the one transistor cell to rely on a driver transistor. Moreover, the column cell operates as a constant current source during the discharge of the bit-line. CEDEC 0.18 μ m CMOS process has been utilized to design the column cell. Therefore, the simulated results show that the designed circuit has been operates successfully to comply with the DRAM.

Original languageEnglish
Pages (from-to)269-272
Number of pages4
JournalJournal of Engineering and Applied Sciences
Volume8
Issue number9
DOIs
Publication statusPublished - 2013

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Data storage equipment
Transistors
Capacitor storage
Networks (circuits)
Capacitors

Keywords

  • 3-transistor
  • 4-bit memory column
  • DRAM
  • DRAM cell
  • Malaysia

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Design of 4-bit memory column dram cell in 0.18 μim CMOS process. / Sedaghati, Nasima; Ibne Reaz, Md. Mamun; Rahman, Labonnah F.; Husain, Hafizah.

In: Journal of Engineering and Applied Sciences, Vol. 8, No. 9, 2013, p. 269-272.

Research output: Contribution to journalArticle

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