Design methodology to achieve good testability of VLSI chips: An industrial perspective

H. H. Lo, W. F. Lee, Md. Mamun Ibne Reaz, N. Hisham, A. Y M Shakaff

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Many of today's Very Large Scale Integration (VLSI) chips are digital design that has hundreds of thousands to millions of transistors per chip. Testing of such large VLSI chips proves to be a challenge. One method of addressing this challenge is the introduction of Design For Test (DFT) features into the VLSI chips. This paper describes an efficient methodology of achieving good testability of VLSI chip using a combination of Register Transfer Level (RTL) coding styles with full scan chain implementation and Automatic Test Pattern Generation (ATPG). This paper also describes the method of sharing of DFT pins associated with scan chain in order to reduce packaging cost due to DFT.

Original languageEnglish
Title of host publication2008 International Conference on Electronic Design, ICED 2008
DOIs
Publication statusPublished - 2008
Event2008 International Conference on Electronic Design, ICED 2008 - Penang
Duration: 1 Dec 20083 Dec 2008

Other

Other2008 International Conference on Electronic Design, ICED 2008
CityPenang
Period1/12/083/12/08

Fingerprint

VLSI circuits
Microprocessor chips
Automatic test pattern generation
Packaging
Transistors
Testing
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Lo, H. H., Lee, W. F., Ibne Reaz, M. M., Hisham, N., & Shakaff, A. Y. M. (2008). Design methodology to achieve good testability of VLSI chips: An industrial perspective. In 2008 International Conference on Electronic Design, ICED 2008 [4786782] https://doi.org/10.1109/ICED.2008.4786782

Design methodology to achieve good testability of VLSI chips : An industrial perspective. / Lo, H. H.; Lee, W. F.; Ibne Reaz, Md. Mamun; Hisham, N.; Shakaff, A. Y M.

2008 International Conference on Electronic Design, ICED 2008. 2008. 4786782.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lo, HH, Lee, WF, Ibne Reaz, MM, Hisham, N & Shakaff, AYM 2008, Design methodology to achieve good testability of VLSI chips: An industrial perspective. in 2008 International Conference on Electronic Design, ICED 2008., 4786782, 2008 International Conference on Electronic Design, ICED 2008, Penang, 1/12/08. https://doi.org/10.1109/ICED.2008.4786782
Lo HH, Lee WF, Ibne Reaz MM, Hisham N, Shakaff AYM. Design methodology to achieve good testability of VLSI chips: An industrial perspective. In 2008 International Conference on Electronic Design, ICED 2008. 2008. 4786782 https://doi.org/10.1109/ICED.2008.4786782
Lo, H. H. ; Lee, W. F. ; Ibne Reaz, Md. Mamun ; Hisham, N. ; Shakaff, A. Y M. / Design methodology to achieve good testability of VLSI chips : An industrial perspective. 2008 International Conference on Electronic Design, ICED 2008. 2008.
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