Design and optimization of the power consumption in 16-bits shift register using single edge triggered D-flip-flop

Mohammad Shakeri, Md. Mamun Ibne Reaz, Labonnah F. Rahman, Fazida Hanim Hashim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Designing the low power devices are becoming very important field of research due to the increment of the number of portable devices. In this research, 16-bits shift register circuit design method is proposed using Single Edge Triggered (SET) D-Flip-flop. Moreover, a comparison study between the conventional circuit design and modified design is presented. The proposed circuit is designed using CEDEC 0.18 urn CMOS process. The simulated results show that SET D-FF circuit required lower power than the conventional shift register circuit. However, the conventional circuit required 16-transistors and the proposed design required 10-transistors. Therefore, 10-transistors SET D-flip-flop is the better option for 16-bits shift register.

Original languageEnglish
Pages (from-to)38-43
Number of pages6
JournalJournal of Engineering and Applied Sciences
Volume8
Issue number2
DOIs
Publication statusPublished - 2013

Fingerprint

Shift registers
Flip flop circuits
Electric power utilization
Networks (circuits)
Transistors

Keywords

  • Conventional circuit
  • Portable applications
  • SET D-FF
  • Shift register
  • Transister

ASJC Scopus subject areas

  • Engineering(all)

Cite this

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