Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor

A. H. Afifah Maheran, P. Susthitha Menon N V Visvanathan, I. Ahmad, S. Shaari, H. A. Elgomati, F. Salehuddin

Research output: Contribution to journalArticle

19 Citations (Scopus)

Abstract

In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.

Original languageEnglish
Article number012026
JournalJournal of Physics: Conference Series
Volume431
Issue number1
DOIs
Publication statusPublished - 2013

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transistors
optimization
metals
Taguchi methods
analysis of variance
experiment design
titanium oxides
threshold voltage
simulators
specifications
tungsten
signal to noise ratios
projection

ASJC Scopus subject areas

  • Physics and Astronomy(all)

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Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor. / Afifah Maheran, A. H.; N V Visvanathan, P. Susthitha Menon; Ahmad, I.; Shaari, S.; Elgomati, H. A.; Salehuddin, F.

In: Journal of Physics: Conference Series, Vol. 431, No. 1, 012026, 2013.

Research output: Contribution to journalArticle

Afifah Maheran, A. H. ; N V Visvanathan, P. Susthitha Menon ; Ahmad, I. ; Shaari, S. ; Elgomati, H. A. ; Salehuddin, F. / Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor. In: Journal of Physics: Conference Series. 2013 ; Vol. 431, No. 1.
@article{11d5db9f98394beca3c152f9a622f0f4,
title = "Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor",
abstract = "In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.",
author = "{Afifah Maheran}, {A. H.} and {N V Visvanathan}, {P. Susthitha Menon} and I. Ahmad and S. Shaari and Elgomati, {H. A.} and F. Salehuddin",
year = "2013",
doi = "10.1088/1742-6596/431/1/012026",
language = "English",
volume = "431",
journal = "Journal of Physics: Conference Series",
issn = "1742-6588",
publisher = "IOP Publishing Ltd.",
number = "1",

}

TY - JOUR

T1 - Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor

AU - Afifah Maheran, A. H.

AU - N V Visvanathan, P. Susthitha Menon

AU - Ahmad, I.

AU - Shaari, S.

AU - Elgomati, H. A.

AU - Salehuddin, F.

PY - 2013

Y1 - 2013

N2 - In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.

AB - In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.

UR - http://www.scopus.com/inward/record.url?scp=84876950567&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84876950567&partnerID=8YFLogxK

U2 - 10.1088/1742-6596/431/1/012026

DO - 10.1088/1742-6596/431/1/012026

M3 - Article

VL - 431

JO - Journal of Physics: Conference Series

JF - Journal of Physics: Conference Series

SN - 1742-6588

IS - 1

M1 - 012026

ER -