Design and implementation of a data compression scheme: A partial matching approach

F. Choong, Md. Mamun Ibne Reaz, T. C. Chin, F. Mohd-Yasin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Data compression is an essential process due to the need to reduce the average time required to send messages and reduce the data size for storage purposes. There is a vital need for lossless compression especially for text and binary compression because it is important to ensure that the restructured text is identical to the original text. The predictive by partial matching (PPM) data compression scheme has set the performance standard in lossless compression throughout the past decade. PPM is chosen as it is capable of very good compression on a variety of data. In this paper, we present the realization of data compression using PPM on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The PPM algorithm for binary data compression was successfully written and modeled in VHDL. The design is followed by the timing analysis and circuit synthesis for the validation, functionality and performance of the designated circuit which supports the practicality, advantages and effectiveness of the proposed hardware realization for the application. The designed was verified using both 16-bit input and 32-bit input. The hardware prototype utilized 1164 logic cells with a maximum system frequency of 95.3 MHz.

Original languageEnglish
Title of host publicationProceedings - Computer Graphics, Imaging and Visualisation: Techniques and Applications, CGIV'06
Pages150-155
Number of pages6
Volume2006
DOIs
Publication statusPublished - 2006
Externally publishedYes
EventInternational Conference on Computer Graphics, Imaging and Visualisation, CGIV'06 - Sydney
Duration: 26 Jul 200628 Jul 2006

Other

OtherInternational Conference on Computer Graphics, Imaging and Visualisation, CGIV'06
CitySydney
Period26/7/0628/7/06

Fingerprint

Data compression
Hardware
Computer hardware description languages
Networks (circuits)
Field programmable gate arrays (FPGA)

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Choong, F., Ibne Reaz, M. M., Chin, T. C., & Mohd-Yasin, F. (2006). Design and implementation of a data compression scheme: A partial matching approach. In Proceedings - Computer Graphics, Imaging and Visualisation: Techniques and Applications, CGIV'06 (Vol. 2006, pp. 150-155). [1663782] https://doi.org/10.1109/CGIV.2006.94

Design and implementation of a data compression scheme : A partial matching approach. / Choong, F.; Ibne Reaz, Md. Mamun; Chin, T. C.; Mohd-Yasin, F.

Proceedings - Computer Graphics, Imaging and Visualisation: Techniques and Applications, CGIV'06. Vol. 2006 2006. p. 150-155 1663782.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Choong, F, Ibne Reaz, MM, Chin, TC & Mohd-Yasin, F 2006, Design and implementation of a data compression scheme: A partial matching approach. in Proceedings - Computer Graphics, Imaging and Visualisation: Techniques and Applications, CGIV'06. vol. 2006, 1663782, pp. 150-155, International Conference on Computer Graphics, Imaging and Visualisation, CGIV'06, Sydney, 26/7/06. https://doi.org/10.1109/CGIV.2006.94
Choong F, Ibne Reaz MM, Chin TC, Mohd-Yasin F. Design and implementation of a data compression scheme: A partial matching approach. In Proceedings - Computer Graphics, Imaging and Visualisation: Techniques and Applications, CGIV'06. Vol. 2006. 2006. p. 150-155. 1663782 https://doi.org/10.1109/CGIV.2006.94
Choong, F. ; Ibne Reaz, Md. Mamun ; Chin, T. C. ; Mohd-Yasin, F. / Design and implementation of a data compression scheme : A partial matching approach. Proceedings - Computer Graphics, Imaging and Visualisation: Techniques and Applications, CGIV'06. Vol. 2006 2006. pp. 150-155
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