Current sensor and compatible test processor for IDDQ testing of integrated circuits

M. S. Amin, Md. Mamun Ibne Reaz, Mohd Marufuzzaman

Research output: Contribution to journalArticle

Abstract

The present state and next state of sequential circuits are not independently controllable and observable. As such, the testing of sequential circuit is complicated. This study presents an approach to design and develop a VLSI system for the simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits. The research involves the design of an interfacing unit on PCB containing interfacing circuits for parallel data exchange between a test processor and a microcomputer. This allows IDDQ measurement for every vector used for logic testing, performing logic testing simultaneously, providing a promising IDDQ fault coverage and reducing substantially the time and cost of testing. Three basic test development strategies are considered. They are functional test development, structural test development and physical defect test development. Mixed-mode testing facility is adopted to enhance the performance and reduce the testing time. The simulation result shows that the presence of the sensor does not degrade the normal operation of the CUT.

Original languageEnglish
Pages (from-to)152-154
Number of pages3
JournalJournal of Engineering and Applied Sciences
Volume7
Issue number2
DOIs
Publication statusPublished - 2012

Fingerprint

Integrated circuits
Sensors
Testing
Sequential circuits
Electronic data interchange
Polychlorinated biphenyls
Microcomputers
Defects
Networks (circuits)
Costs

Keywords

  • CMOS
  • Current sensor
  • IDDQ testing
  • Malaysia
  • Physical defeat
  • Test processor

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Current sensor and compatible test processor for IDDQ testing of integrated circuits. / Amin, M. S.; Ibne Reaz, Md. Mamun; Marufuzzaman, Mohd.

In: Journal of Engineering and Applied Sciences, Vol. 7, No. 2, 2012, p. 152-154.

Research output: Contribution to journalArticle

@article{c26f420f6a1c435298d2cd1814a8bf9d,
title = "Current sensor and compatible test processor for IDDQ testing of integrated circuits",
abstract = "The present state and next state of sequential circuits are not independently controllable and observable. As such, the testing of sequential circuit is complicated. This study presents an approach to design and develop a VLSI system for the simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits. The research involves the design of an interfacing unit on PCB containing interfacing circuits for parallel data exchange between a test processor and a microcomputer. This allows IDDQ measurement for every vector used for logic testing, performing logic testing simultaneously, providing a promising IDDQ fault coverage and reducing substantially the time and cost of testing. Three basic test development strategies are considered. They are functional test development, structural test development and physical defect test development. Mixed-mode testing facility is adopted to enhance the performance and reduce the testing time. The simulation result shows that the presence of the sensor does not degrade the normal operation of the CUT.",
keywords = "CMOS, Current sensor, IDDQ testing, Malaysia, Physical defeat, Test processor",
author = "Amin, {M. S.} and {Ibne Reaz}, {Md. Mamun} and Mohd Marufuzzaman",
year = "2012",
doi = "10.3923/jeasci.2012.152.154",
language = "English",
volume = "7",
pages = "152--154",
journal = "Journal of Engineering and Applied Sciences",
issn = "1816-949X",
publisher = "Medwell Journals",
number = "2",

}

TY - JOUR

T1 - Current sensor and compatible test processor for IDDQ testing of integrated circuits

AU - Amin, M. S.

AU - Ibne Reaz, Md. Mamun

AU - Marufuzzaman, Mohd

PY - 2012

Y1 - 2012

N2 - The present state and next state of sequential circuits are not independently controllable and observable. As such, the testing of sequential circuit is complicated. This study presents an approach to design and develop a VLSI system for the simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits. The research involves the design of an interfacing unit on PCB containing interfacing circuits for parallel data exchange between a test processor and a microcomputer. This allows IDDQ measurement for every vector used for logic testing, performing logic testing simultaneously, providing a promising IDDQ fault coverage and reducing substantially the time and cost of testing. Three basic test development strategies are considered. They are functional test development, structural test development and physical defect test development. Mixed-mode testing facility is adopted to enhance the performance and reduce the testing time. The simulation result shows that the presence of the sensor does not degrade the normal operation of the CUT.

AB - The present state and next state of sequential circuits are not independently controllable and observable. As such, the testing of sequential circuit is complicated. This study presents an approach to design and develop a VLSI system for the simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits. The research involves the design of an interfacing unit on PCB containing interfacing circuits for parallel data exchange between a test processor and a microcomputer. This allows IDDQ measurement for every vector used for logic testing, performing logic testing simultaneously, providing a promising IDDQ fault coverage and reducing substantially the time and cost of testing. Three basic test development strategies are considered. They are functional test development, structural test development and physical defect test development. Mixed-mode testing facility is adopted to enhance the performance and reduce the testing time. The simulation result shows that the presence of the sensor does not degrade the normal operation of the CUT.

KW - CMOS

KW - Current sensor

KW - IDDQ testing

KW - Malaysia

KW - Physical defeat

KW - Test processor

UR - http://www.scopus.com/inward/record.url?scp=84883288677&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883288677&partnerID=8YFLogxK

U2 - 10.3923/jeasci.2012.152.154

DO - 10.3923/jeasci.2012.152.154

M3 - Article

VL - 7

SP - 152

EP - 154

JO - Journal of Engineering and Applied Sciences

JF - Journal of Engineering and Applied Sciences

SN - 1816-949X

IS - 2

ER -