Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method

A. H. Afifah Maheran, P. Susthitha Menon N V Visvanathan, I. Ahmad, F. Salehuddin, A. S. Mohd, Z. A. Noor, H. A. Elgomati

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-To-Noise Ratio (SNR) analysis uses the Nominal-The-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-The-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/μm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS).

Original languageEnglish
Pages (from-to)137-141
Number of pages5
JournalJournal of Telecommunication, Electronic and Computer Engineering
Volume9
Issue number2-7
Publication statusPublished - 2017

Fingerprint

Taguchi methods
Threshold voltage
Leakage currents
Signal to noise ratio
Transistors
Titanium dioxide
Tungsten
Permittivity
Semiconductor materials
Metals

Keywords

  • 22 Nm NMOS Tio2/Wsix
  • High-K/Metal Gate
  • Leakage Current
  • Taguchi Method.
  • Threshold Voltage

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method. / Afifah Maheran, A. H.; N V Visvanathan, P. Susthitha Menon; Ahmad, I.; Salehuddin, F.; Mohd, A. S.; Noor, Z. A.; Elgomati, H. A.

In: Journal of Telecommunication, Electronic and Computer Engineering, Vol. 9, No. 2-7, 2017, p. 137-141.

Research output: Contribution to journalArticle

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AU - N V Visvanathan, P. Susthitha Menon

AU - Ahmad, I.

AU - Salehuddin, F.

AU - Mohd, A. S.

AU - Noor, Z. A.

AU - Elgomati, H. A.

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N2 - In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-To-Noise Ratio (SNR) analysis uses the Nominal-The-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-The-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/μm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS).

AB - In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-To-Noise Ratio (SNR) analysis uses the Nominal-The-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-The-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/μm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS).

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