### Abstract

In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO_{2}) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-To-Noise Ratio (SNR) analysis uses the Nominal-The-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-The-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/μm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS).

Original language | English |
---|---|

Pages (from-to) | 137-141 |

Number of pages | 5 |

Journal | Journal of Telecommunication, Electronic and Computer Engineering |

Volume | 9 |

Issue number | 2-7 |

Publication status | Published - 2017 |

### Fingerprint

### Keywords

- 22 Nm NMOS Tio2/Wsix
- High-K/Metal Gate
- Leakage Current
- Taguchi Method.
- Threshold Voltage

### ASJC Scopus subject areas

- Hardware and Architecture
- Computer Networks and Communications
- Electrical and Electronic Engineering

### Cite this

*Journal of Telecommunication, Electronic and Computer Engineering*,

*9*(2-7), 137-141.

**Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method.** / Afifah Maheran, A. H.; N V Visvanathan, P. Susthitha Menon; Ahmad, I.; Salehuddin, F.; Mohd, A. S.; Noor, Z. A.; Elgomati, H. A.

Research output: Contribution to journal › Article

*Journal of Telecommunication, Electronic and Computer Engineering*, vol. 9, no. 2-7, pp. 137-141.

}

TY - JOUR

T1 - Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method

AU - Afifah Maheran, A. H.

AU - N V Visvanathan, P. Susthitha Menon

AU - Ahmad, I.

AU - Salehuddin, F.

AU - Mohd, A. S.

AU - Noor, Z. A.

AU - Elgomati, H. A.

PY - 2017

Y1 - 2017

N2 - In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-To-Noise Ratio (SNR) analysis uses the Nominal-The-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-The-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/μm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS).

AB - In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-To-Noise Ratio (SNR) analysis uses the Nominal-The-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-The-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/μm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS).

KW - 22 Nm NMOS Tio2/Wsix

KW - High-K/Metal Gate

KW - Leakage Current

KW - Taguchi Method.

KW - Threshold Voltage

UR - http://www.scopus.com/inward/record.url?scp=85032895208&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85032895208&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:85032895208

VL - 9

SP - 137

EP - 141

JO - Journal of Telecommunication, Electronic and Computer Engineering

JF - Journal of Telecommunication, Electronic and Computer Engineering

SN - 2180-1843

IS - 2-7

ER -