CMOS phase frequency detector for high speed applications

Nesreen Mahmoud Hammam Ismail, Masuri Othman

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)

    Abstract

    A simple new phase frequency detector design is presented in this paper. Falling-Edge PFD uses only 12 transistors and preserves the main characteristics of the conventional PFD. It is implemented using Silterra 0.18 μm CMOS Process. It consumes 6.6 μW when operating at 50 MHz clock frequency with 1.8V voltage supply. It has free dead zone and operates up to 2.5 GHz. It can be used in high speed and low power consumption applications. A single ended switch at source charge pump is presented as well. It is compatible with the FE-PFD outputs characteristics.

    Original languageEnglish
    Title of host publication2009 4th International Design and Test Workshop, IDT 2009
    DOIs
    Publication statusPublished - 2009
    Event2009 4th International Design and Test Workshop, IDT 2009 - Riyadh
    Duration: 15 Nov 200917 Nov 2009

    Other

    Other2009 4th International Design and Test Workshop, IDT 2009
    CityRiyadh
    Period15/11/0917/11/09

    Fingerprint

    Clocks
    Transistors
    Electric power utilization
    Switches
    Pumps
    Detectors
    Electric potential

    Keywords

    • Charge pump
    • High speed integrated circuits
    • Phase frequency detector
    • Phase locked loop

    ASJC Scopus subject areas

    • Computer Science(all)
    • Control and Systems Engineering

    Cite this

    Ismail, N. M. H., & Othman, M. (2009). CMOS phase frequency detector for high speed applications. In 2009 4th International Design and Test Workshop, IDT 2009 [5404165] https://doi.org/10.1109/IDT.2009.5404165

    CMOS phase frequency detector for high speed applications. / Ismail, Nesreen Mahmoud Hammam; Othman, Masuri.

    2009 4th International Design and Test Workshop, IDT 2009. 2009. 5404165.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Ismail, NMH & Othman, M 2009, CMOS phase frequency detector for high speed applications. in 2009 4th International Design and Test Workshop, IDT 2009., 5404165, 2009 4th International Design and Test Workshop, IDT 2009, Riyadh, 15/11/09. https://doi.org/10.1109/IDT.2009.5404165
    Ismail NMH, Othman M. CMOS phase frequency detector for high speed applications. In 2009 4th International Design and Test Workshop, IDT 2009. 2009. 5404165 https://doi.org/10.1109/IDT.2009.5404165
    Ismail, Nesreen Mahmoud Hammam ; Othman, Masuri. / CMOS phase frequency detector for high speed applications. 2009 4th International Design and Test Workshop, IDT 2009. 2009.
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    title = "CMOS phase frequency detector for high speed applications",
    abstract = "A simple new phase frequency detector design is presented in this paper. Falling-Edge PFD uses only 12 transistors and preserves the main characteristics of the conventional PFD. It is implemented using Silterra 0.18 μm CMOS Process. It consumes 6.6 μW when operating at 50 MHz clock frequency with 1.8V voltage supply. It has free dead zone and operates up to 2.5 GHz. It can be used in high speed and low power consumption applications. A single ended switch at source charge pump is presented as well. It is compatible with the FE-PFD outputs characteristics.",
    keywords = "Charge pump, High speed integrated circuits, Phase frequency detector, Phase locked loop",
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    KW - Phase locked loop

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