CMOS high-speed 1/14 dynamic frequency divider

Queennie Lim Suan Imm, Albert Victor Kordesch, Burhanuddin Yeop Majlis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A dynamic frequency divider is capable of operating at twice the frequency of a static divider. The clocked dynamic inverter type flip-flop divider isadopted for use as a dynamic frequency divider. The dynamic divider is based on the C2MOS (Clocked CMOS) master-slave concept. The flip-flops are clocked by a single clock input. The dynamic divider was designed to divide its input by 2n where n denotes the number of divider stages. This synchronous dynamic divider can divide a sine wave input at a maximum frequency of 2.7GHz. Our dynamic divider is implemented on the Silterra 0.18um CMOS technology, and it operates with a 1.8V power supply. To demonstrate the capability of the dynamic divider, this paper will compare the dynamic divider to a static 2 n divider. The dynamic divider is faster and has about half the device complexity of a static divider.

Original languageEnglish
Title of host publication2006 International RF and Microwave Conference, (RFM) Proceedings
Pages220-224
Number of pages5
DOIs
Publication statusPublished - 2006
Event2006 International RF and Microwave Conference, RFM - Putrajaya
Duration: 12 Sep 200614 Sep 2006

Other

Other2006 International RF and Microwave Conference, RFM
CityPutrajaya
Period12/9/0614/9/06

Fingerprint

Flip flop circuits
Clocks

Keywords

  • Dynamic frequency divider, radio frequency, CMOS.

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Suan Imm, Q. L., Kordesch, A. V., & Yeop Majlis, B. (2006). CMOS high-speed 1/14 dynamic frequency divider. In 2006 International RF and Microwave Conference, (RFM) Proceedings (pp. 220-224). [4133588] https://doi.org/10.1109/RFM.2006.331073

CMOS high-speed 1/14 dynamic frequency divider. / Suan Imm, Queennie Lim; Kordesch, Albert Victor; Yeop Majlis, Burhanuddin.

2006 International RF and Microwave Conference, (RFM) Proceedings. 2006. p. 220-224 4133588.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suan Imm, QL, Kordesch, AV & Yeop Majlis, B 2006, CMOS high-speed 1/14 dynamic frequency divider. in 2006 International RF and Microwave Conference, (RFM) Proceedings., 4133588, pp. 220-224, 2006 International RF and Microwave Conference, RFM, Putrajaya, 12/9/06. https://doi.org/10.1109/RFM.2006.331073
Suan Imm QL, Kordesch AV, Yeop Majlis B. CMOS high-speed 1/14 dynamic frequency divider. In 2006 International RF and Microwave Conference, (RFM) Proceedings. 2006. p. 220-224. 4133588 https://doi.org/10.1109/RFM.2006.331073
Suan Imm, Queennie Lim ; Kordesch, Albert Victor ; Yeop Majlis, Burhanuddin. / CMOS high-speed 1/14 dynamic frequency divider. 2006 International RF and Microwave Conference, (RFM) Proceedings. 2006. pp. 220-224
@inproceedings{4cb9fed744ab4bd9b9f5154d0608292d,
title = "CMOS high-speed 1/14 dynamic frequency divider",
abstract = "A dynamic frequency divider is capable of operating at twice the frequency of a static divider. The clocked dynamic inverter type flip-flop divider isadopted for use as a dynamic frequency divider. The dynamic divider is based on the C2MOS (Clocked CMOS) master-slave concept. The flip-flops are clocked by a single clock input. The dynamic divider was designed to divide its input by 2n where n denotes the number of divider stages. This synchronous dynamic divider can divide a sine wave input at a maximum frequency of 2.7GHz. Our dynamic divider is implemented on the Silterra 0.18um CMOS technology, and it operates with a 1.8V power supply. To demonstrate the capability of the dynamic divider, this paper will compare the dynamic divider to a static 2 n divider. The dynamic divider is faster and has about half the device complexity of a static divider.",
keywords = "Dynamic frequency divider, radio frequency, CMOS.",
author = "{Suan Imm}, {Queennie Lim} and Kordesch, {Albert Victor} and {Yeop Majlis}, Burhanuddin",
year = "2006",
doi = "10.1109/RFM.2006.331073",
language = "English",
isbn = "0780397444",
pages = "220--224",
booktitle = "2006 International RF and Microwave Conference, (RFM) Proceedings",

}

TY - GEN

T1 - CMOS high-speed 1/14 dynamic frequency divider

AU - Suan Imm, Queennie Lim

AU - Kordesch, Albert Victor

AU - Yeop Majlis, Burhanuddin

PY - 2006

Y1 - 2006

N2 - A dynamic frequency divider is capable of operating at twice the frequency of a static divider. The clocked dynamic inverter type flip-flop divider isadopted for use as a dynamic frequency divider. The dynamic divider is based on the C2MOS (Clocked CMOS) master-slave concept. The flip-flops are clocked by a single clock input. The dynamic divider was designed to divide its input by 2n where n denotes the number of divider stages. This synchronous dynamic divider can divide a sine wave input at a maximum frequency of 2.7GHz. Our dynamic divider is implemented on the Silterra 0.18um CMOS technology, and it operates with a 1.8V power supply. To demonstrate the capability of the dynamic divider, this paper will compare the dynamic divider to a static 2 n divider. The dynamic divider is faster and has about half the device complexity of a static divider.

AB - A dynamic frequency divider is capable of operating at twice the frequency of a static divider. The clocked dynamic inverter type flip-flop divider isadopted for use as a dynamic frequency divider. The dynamic divider is based on the C2MOS (Clocked CMOS) master-slave concept. The flip-flops are clocked by a single clock input. The dynamic divider was designed to divide its input by 2n where n denotes the number of divider stages. This synchronous dynamic divider can divide a sine wave input at a maximum frequency of 2.7GHz. Our dynamic divider is implemented on the Silterra 0.18um CMOS technology, and it operates with a 1.8V power supply. To demonstrate the capability of the dynamic divider, this paper will compare the dynamic divider to a static 2 n divider. The dynamic divider is faster and has about half the device complexity of a static divider.

KW - Dynamic frequency divider, radio frequency, CMOS.

UR - http://www.scopus.com/inward/record.url?scp=46249094769&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=46249094769&partnerID=8YFLogxK

U2 - 10.1109/RFM.2006.331073

DO - 10.1109/RFM.2006.331073

M3 - Conference contribution

SN - 0780397444

SN - 9780780397446

SP - 220

EP - 224

BT - 2006 International RF and Microwave Conference, (RFM) Proceedings

ER -