Characterization and optimizations of silicide thickness in 45nm pMOS device

F. Salehuddin, I. Ahmad, F. A. Hamid, Azami Zaharim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLAS's simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is -0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm.

Original languageEnglish
Title of host publication2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings
Pages300-304
Number of pages5
DOIs
Publication statusPublished - 2010
Event2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010 - Kuala Lumpur
Duration: 12 Apr 201013 Apr 2010

Other

Other2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010
CityKuala Lumpur
Period12/4/1013/4/10

Fingerprint

Taguchi methods
Semiconductor materials
Electrodes
Growth temperature
Threshold voltage
Polysilicon
Simulators
Fabrication
Oxides
Experiments
Temperature

Keywords

  • 45nm pMOS
  • Cobalt salicide
  • Optimization
  • Taguchi method

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Salehuddin, F., Ahmad, I., Hamid, F. A., & Zaharim, A. (2010). Characterization and optimizations of silicide thickness in 45nm pMOS device. In 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings (pp. 300-304). [5503054] https://doi.org/10.1109/ICEDSA.2010.5503054

Characterization and optimizations of silicide thickness in 45nm pMOS device. / Salehuddin, F.; Ahmad, I.; Hamid, F. A.; Zaharim, Azami.

2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. 2010. p. 300-304 5503054.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Salehuddin, F, Ahmad, I, Hamid, FA & Zaharim, A 2010, Characterization and optimizations of silicide thickness in 45nm pMOS device. in 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings., 5503054, pp. 300-304, 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010, Kuala Lumpur, 12/4/10. https://doi.org/10.1109/ICEDSA.2010.5503054
Salehuddin F, Ahmad I, Hamid FA, Zaharim A. Characterization and optimizations of silicide thickness in 45nm pMOS device. In 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. 2010. p. 300-304. 5503054 https://doi.org/10.1109/ICEDSA.2010.5503054
Salehuddin, F. ; Ahmad, I. ; Hamid, F. A. ; Zaharim, Azami. / Characterization and optimizations of silicide thickness in 45nm pMOS device. 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. 2010. pp. 300-304
@inproceedings{3c47ff647984466cbce87bd50b8409b9,
title = "Characterization and optimizations of silicide thickness in 45nm pMOS device",
abstract = "The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLAS's simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is -0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm.",
keywords = "45nm pMOS, Cobalt salicide, Optimization, Taguchi method",
author = "F. Salehuddin and I. Ahmad and Hamid, {F. A.} and Azami Zaharim",
year = "2010",
doi = "10.1109/ICEDSA.2010.5503054",
language = "English",
isbn = "9781424466320",
pages = "300--304",
booktitle = "2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings",

}

TY - GEN

T1 - Characterization and optimizations of silicide thickness in 45nm pMOS device

AU - Salehuddin, F.

AU - Ahmad, I.

AU - Hamid, F. A.

AU - Zaharim, Azami

PY - 2010

Y1 - 2010

N2 - The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLAS's simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is -0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm.

AB - The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLAS's simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is -0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm.

KW - 45nm pMOS

KW - Cobalt salicide

KW - Optimization

KW - Taguchi method

UR - http://www.scopus.com/inward/record.url?scp=77955297325&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955297325&partnerID=8YFLogxK

U2 - 10.1109/ICEDSA.2010.5503054

DO - 10.1109/ICEDSA.2010.5503054

M3 - Conference contribution

AN - SCOPUS:77955297325

SN - 9781424466320

SP - 300

EP - 304

BT - 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings

ER -