An enhancement of decimation process using fast Cascaded Integrator Comb (CIC) filter

Rozita Teymourzadeh, Masuri Bin Othman

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in to Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.

    Original languageEnglish
    Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
    Pages811-815
    Number of pages5
    DOIs
    Publication statusPublished - 2006
    Event2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006 - Kuala Lumpur
    Duration: 29 Nov 20061 Dec 2006

    Other

    Other2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006
    CityKuala Lumpur
    Period29/11/061/12/06

    Fingerprint

    Comb filters
    Sampling
    Computer hardware description languages
    Field programmable gate arrays (FPGA)
    Electric power utilization
    Silicon

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Teymourzadeh, R., & Othman, M. B. (2006). An enhancement of decimation process using fast Cascaded Integrator Comb (CIC) filter. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 811-815). [4266732] https://doi.org/10.1109/SMELEC.2006.380749

    An enhancement of decimation process using fast Cascaded Integrator Comb (CIC) filter. / Teymourzadeh, Rozita; Othman, Masuri Bin.

    IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. p. 811-815 4266732.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Teymourzadeh, R & Othman, MB 2006, An enhancement of decimation process using fast Cascaded Integrator Comb (CIC) filter. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 4266732, pp. 811-815, 2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006, Kuala Lumpur, 29/11/06. https://doi.org/10.1109/SMELEC.2006.380749
    Teymourzadeh R, Othman MB. An enhancement of decimation process using fast Cascaded Integrator Comb (CIC) filter. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. p. 811-815. 4266732 https://doi.org/10.1109/SMELEC.2006.380749
    Teymourzadeh, Rozita ; Othman, Masuri Bin. / An enhancement of decimation process using fast Cascaded Integrator Comb (CIC) filter. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. pp. 811-815
    @inproceedings{31d7c547e2094081b219d439995070bd,
    title = "An enhancement of decimation process using fast Cascaded Integrator Comb (CIC) filter",
    abstract = "The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in to Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.",
    author = "Rozita Teymourzadeh and Othman, {Masuri Bin}",
    year = "2006",
    doi = "10.1109/SMELEC.2006.380749",
    language = "English",
    isbn = "0780397312",
    pages = "811--815",
    booktitle = "IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE",

    }

    TY - GEN

    T1 - An enhancement of decimation process using fast Cascaded Integrator Comb (CIC) filter

    AU - Teymourzadeh, Rozita

    AU - Othman, Masuri Bin

    PY - 2006

    Y1 - 2006

    N2 - The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in to Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.

    AB - The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in to Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.

    UR - http://www.scopus.com/inward/record.url?scp=35148877313&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=35148877313&partnerID=8YFLogxK

    U2 - 10.1109/SMELEC.2006.380749

    DO - 10.1109/SMELEC.2006.380749

    M3 - Conference contribution

    SN - 0780397312

    SN - 9780780397316

    SP - 811

    EP - 815

    BT - IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

    ER -