An efficient fault syndromes simulator for SRAM memories

Wan Zuha Wan Hasan, Izhal Abd Halin, Roslina Mohd Sidek, Masuri Othman

    Research output: Contribution to journalArticle

    2 Citations (Scopus)

    Abstract

    Testing and diagnosis techniques play a key role in the advance of semiconductor memory technology. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. At present, March test algorithm is used to detect and diagnose all faults related to Random Access Memories. However, the test and diagnosis process are mainly done manually. Due to this, a systematic approach for developing and evaluating memory test algorithm is required. This work is focused on incorporating the March based test algorithm using a software simulator tool for implementing a fast and systematic memory testing algorithm. The simulator allows a user through a GUI to select a March based test algorithm depending on the desired fault coverage and diagnostic resolution. Experimental results show that using the simulator for testing is more efficient than that of the traditional testing algorithm. This new simulator makes it possible for a detailed list of stuck-at faults, transition faults and coupling faults covered by each algorithm and its percentage to be displayed after a set of test algorithms has been chosen. The percentage of diagnostic resolution is also displayed. This proves that the simulator reduces the trade-off between test time, fault coverage and diagnostic resolution. Moreover, the chosen algorithm can be applied to incorporate with memory built-in self-test and diagnosis, to have a better fault coverage and diagnostic resolution. Universities and industry involved in memory Built- in-Self test, Built-in-Self repair and Built-in-Self diagnose will benefit by saving a few years on researching an efficient algorithm to be implemented in their designs.

    Original languageEnglish
    Pages (from-to)639-646
    Number of pages8
    JournalIEICE Transactions on Electronics
    VolumeE92-C
    Issue number5
    DOIs
    Publication statusPublished - 2009

    Fingerprint

    Static random access storage
    Simulators
    Data storage equipment
    Testing
    Built-in self test
    Graphical user interfaces
    Repair
    Semiconductor materials

    Keywords

    • Automated march-based test algorithm
    • Built-in self-diagnosis (BISD)
    • Built-in self-test (BIST)
    • Coupling faults
    • Diagnosis
    • SRAM
    • Stuck-at faults March test algorithm
    • Testing

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Cite this

    Wan Hasan, W. Z., Halin, I. A., Sidek, R. M., & Othman, M. (2009). An efficient fault syndromes simulator for SRAM memories. IEICE Transactions on Electronics, E92-C(5), 639-646. https://doi.org/10.1587/transele.E92.C.639

    An efficient fault syndromes simulator for SRAM memories. / Wan Hasan, Wan Zuha; Halin, Izhal Abd; Sidek, Roslina Mohd; Othman, Masuri.

    In: IEICE Transactions on Electronics, Vol. E92-C, No. 5, 2009, p. 639-646.

    Research output: Contribution to journalArticle

    Wan Hasan, WZ, Halin, IA, Sidek, RM & Othman, M 2009, 'An efficient fault syndromes simulator for SRAM memories', IEICE Transactions on Electronics, vol. E92-C, no. 5, pp. 639-646. https://doi.org/10.1587/transele.E92.C.639
    Wan Hasan, Wan Zuha ; Halin, Izhal Abd ; Sidek, Roslina Mohd ; Othman, Masuri. / An efficient fault syndromes simulator for SRAM memories. In: IEICE Transactions on Electronics. 2009 ; Vol. E92-C, No. 5. pp. 639-646.
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