A study using two stage NBTI model for 32 nm high-k PMOSFET

H. Hussin, M. Muhamad, Y. Abdul Wahab, S. Shahabuddin, N. Soin, Muhammad Faiz Bukhori

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Kinetics of E'centers and threshold voltage shift, (ΔVth) of High-K Metal Gate Stacks has been comprehensively studied using two - stage Negative Bias Temperature Instability (NBTI) model. To effectively study the kinetics of E' centers, the two stage model was simulated with stage one only and then simulated in both stages. The evolution of trap kinetics was further investigated by varying parametric of energy barriers. We found that the model capable to explain the hole trapping and de-trapping mechanism occurs in NBTI degradation particularly on the transformation between hole traps into a more permanent form which explain the process of de-passivation of interface trap precursor as triggered by hole captured at an E' center precursor.

Original languageEnglish
Title of host publication2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs
Publication statusPublished - 2013
Event2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong
Duration: 3 Jun 20135 Jun 2013

Other

Other2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
CityHong Kong
Period3/6/135/6/13

Fingerprint

Kinetics
Hole traps
Energy barriers
Threshold voltage
Passivation
Degradation
Metals
Negative bias temperature instability

Keywords

  • E' Centers
  • High-k PMOSFET
  • Hole trapping and de-trapping
  • NBTI
  • Two stage model
  • Vth Degradation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Hussin, H., Muhamad, M., Abdul Wahab, Y., Shahabuddin, S., Soin, N., & Bukhori, M. F. (2013). A study using two stage NBTI model for 32 nm high-k PMOSFET. In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 [6628108] https://doi.org/10.1109/EDSSC.2013.6628108

A study using two stage NBTI model for 32 nm high-k PMOSFET. / Hussin, H.; Muhamad, M.; Abdul Wahab, Y.; Shahabuddin, S.; Soin, N.; Bukhori, Muhammad Faiz.

2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013. 6628108.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hussin, H, Muhamad, M, Abdul Wahab, Y, Shahabuddin, S, Soin, N & Bukhori, MF 2013, A study using two stage NBTI model for 32 nm high-k PMOSFET. in 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013., 6628108, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, Hong Kong, 3/6/13. https://doi.org/10.1109/EDSSC.2013.6628108
Hussin H, Muhamad M, Abdul Wahab Y, Shahabuddin S, Soin N, Bukhori MF. A study using two stage NBTI model for 32 nm high-k PMOSFET. In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013. 6628108 https://doi.org/10.1109/EDSSC.2013.6628108
Hussin, H. ; Muhamad, M. ; Abdul Wahab, Y. ; Shahabuddin, S. ; Soin, N. ; Bukhori, Muhammad Faiz. / A study using two stage NBTI model for 32 nm high-k PMOSFET. 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013.
@inproceedings{d404a3c887c6498da6164bbf9ece1c97,
title = "A study using two stage NBTI model for 32 nm high-k PMOSFET",
abstract = "Kinetics of E'centers and threshold voltage shift, (ΔVth) of High-K Metal Gate Stacks has been comprehensively studied using two - stage Negative Bias Temperature Instability (NBTI) model. To effectively study the kinetics of E' centers, the two stage model was simulated with stage one only and then simulated in both stages. The evolution of trap kinetics was further investigated by varying parametric of energy barriers. We found that the model capable to explain the hole trapping and de-trapping mechanism occurs in NBTI degradation particularly on the transformation between hole traps into a more permanent form which explain the process of de-passivation of interface trap precursor as triggered by hole captured at an E' center precursor.",
keywords = "E' Centers, High-k PMOSFET, Hole trapping and de-trapping, NBTI, Two stage model, Vth Degradation",
author = "H. Hussin and M. Muhamad and {Abdul Wahab}, Y. and S. Shahabuddin and N. Soin and Bukhori, {Muhammad Faiz}",
year = "2013",
doi = "10.1109/EDSSC.2013.6628108",
language = "English",
isbn = "9781467325233",
booktitle = "2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013",

}

TY - GEN

T1 - A study using two stage NBTI model for 32 nm high-k PMOSFET

AU - Hussin, H.

AU - Muhamad, M.

AU - Abdul Wahab, Y.

AU - Shahabuddin, S.

AU - Soin, N.

AU - Bukhori, Muhammad Faiz

PY - 2013

Y1 - 2013

N2 - Kinetics of E'centers and threshold voltage shift, (ΔVth) of High-K Metal Gate Stacks has been comprehensively studied using two - stage Negative Bias Temperature Instability (NBTI) model. To effectively study the kinetics of E' centers, the two stage model was simulated with stage one only and then simulated in both stages. The evolution of trap kinetics was further investigated by varying parametric of energy barriers. We found that the model capable to explain the hole trapping and de-trapping mechanism occurs in NBTI degradation particularly on the transformation between hole traps into a more permanent form which explain the process of de-passivation of interface trap precursor as triggered by hole captured at an E' center precursor.

AB - Kinetics of E'centers and threshold voltage shift, (ΔVth) of High-K Metal Gate Stacks has been comprehensively studied using two - stage Negative Bias Temperature Instability (NBTI) model. To effectively study the kinetics of E' centers, the two stage model was simulated with stage one only and then simulated in both stages. The evolution of trap kinetics was further investigated by varying parametric of energy barriers. We found that the model capable to explain the hole trapping and de-trapping mechanism occurs in NBTI degradation particularly on the transformation between hole traps into a more permanent form which explain the process of de-passivation of interface trap precursor as triggered by hole captured at an E' center precursor.

KW - E' Centers

KW - High-k PMOSFET

KW - Hole trapping and de-trapping

KW - NBTI

KW - Two stage model

KW - Vth Degradation

UR - http://www.scopus.com/inward/record.url?scp=84890487616&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84890487616&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2013.6628108

DO - 10.1109/EDSSC.2013.6628108

M3 - Conference contribution

SN - 9781467325233

BT - 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

ER -