A single clock cycle MIPS RISC Processor design using VHDL

Md. Mamun Ibne Reaz, Md. Shabiul Islam, Mohd S. Sulaiman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

This paper describes a design methodology of a single clock cycle MIPS RISC Processor using VHDL to ease the description, verification, simulation and hardware realization. The RISC processor has fixed-length of 32-bit instructions based on three different format R-format, I-format and J-format, and 32-bit general-purpose registers with memory word of 32-bit. The MIPS processor is separated into five stages: instruction fetch, instruction decode, execution, data memory and write back. The control unit controls the operations performed in these stages. All the modules in the design are coded in VHDL, as it is very useful tool with its concept of concurrency to cope with the parallelism of digital hardware. The top-level module connects all the stages into a higher level. Once detecting the particular approaches for input, output, main block and different modules, the VHDL descriptions are run through a VHDL simulator, followed by the timing analysis for the validation, functionality and performance of the designated design that demonstrate the effectiveness of the design.

Original languageEnglish
Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
Pages199-203
Number of pages5
Publication statusPublished - 2002
Externally publishedYes
Event2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002 - Penang
Duration: 19 Dec 200221 Dec 2002

Other

Other2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002
CityPenang
Period19/12/0221/12/02

Fingerprint

Computer hardware description languages
Reduced instruction set computing
Clocks
Data storage equipment
Computer hardware
Simulators
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Ibne Reaz, M. M., Islam, M. S., & Sulaiman, M. S. (2002). A single clock cycle MIPS RISC Processor design using VHDL. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 199-203). [1217806]

A single clock cycle MIPS RISC Processor design using VHDL. / Ibne Reaz, Md. Mamun; Islam, Md. Shabiul; Sulaiman, Mohd S.

IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2002. p. 199-203 1217806.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ibne Reaz, MM, Islam, MS & Sulaiman, MS 2002, A single clock cycle MIPS RISC Processor design using VHDL. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 1217806, pp. 199-203, 2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002, Penang, 19/12/02.
Ibne Reaz MM, Islam MS, Sulaiman MS. A single clock cycle MIPS RISC Processor design using VHDL. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2002. p. 199-203. 1217806
Ibne Reaz, Md. Mamun ; Islam, Md. Shabiul ; Sulaiman, Mohd S. / A single clock cycle MIPS RISC Processor design using VHDL. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2002. pp. 199-203
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