A ROM-less direct digital frequency synthesizer based on hybrid polynomial approximation

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4 Citations (Scopus)

Abstract

In this paper, a novel design approach for a phase to sinusoid amplitude converter (PSAC) has been investigated. Two segments have been used to approximate the first sine quadrant. A first linear segment is used to fit the region near the zero point, while a second fourth-order parabolic segment is used to approximate the rest of the sine curve. The phase sample, where the polynomial changed, was chosen in such a way as to achieve the maximum spurious free dynamic range (SFDR). The invented direct digital frequency synthesizer (DDFS) has been encoded in VHDL and post simulation was carried out. The synthesized architecture exhibits a promising result of 90 dBc SFDR. The targeted structure is expected to show advantages for perceptible reduction of hardware resources and power consumption as well as high clock speeds.

Original languageEnglish
Article number812576
JournalScientific World Journal
Volume2014
DOIs
Publication statusPublished - 2014

Fingerprint

Polynomial approximation
Frequency synthesizers
ROM
hardware
Computer hardware description languages
resource
simulation
Clocks
Electric power utilization
Polynomials
Hardware
speed
consumption

ASJC Scopus subject areas

  • Biochemistry, Genetics and Molecular Biology(all)
  • Environmental Science(all)
  • Medicine(all)

Cite this

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title = "A ROM-less direct digital frequency synthesizer based on hybrid polynomial approximation",
abstract = "In this paper, a novel design approach for a phase to sinusoid amplitude converter (PSAC) has been investigated. Two segments have been used to approximate the first sine quadrant. A first linear segment is used to fit the region near the zero point, while a second fourth-order parabolic segment is used to approximate the rest of the sine curve. The phase sample, where the polynomial changed, was chosen in such a way as to achieve the maximum spurious free dynamic range (SFDR). The invented direct digital frequency synthesizer (DDFS) has been encoded in VHDL and post simulation was carried out. The synthesized architecture exhibits a promising result of 90 dBc SFDR. The targeted structure is expected to show advantages for perceptible reduction of hardware resources and power consumption as well as high clock speeds.",
author = "Omran, {Qahtan Khalaf} and Islam, {Mohammad Tariqul} and Norbahiah Misran and Faruque, {Mohammad Rashed Iqbal}",
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AU - Omran, Qahtan Khalaf

AU - Islam, Mohammad Tariqul

AU - Misran, Norbahiah

AU - Faruque, Mohammad Rashed Iqbal

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AB - In this paper, a novel design approach for a phase to sinusoid amplitude converter (PSAC) has been investigated. Two segments have been used to approximate the first sine quadrant. A first linear segment is used to fit the region near the zero point, while a second fourth-order parabolic segment is used to approximate the rest of the sine curve. The phase sample, where the polynomial changed, was chosen in such a way as to achieve the maximum spurious free dynamic range (SFDR). The invented direct digital frequency synthesizer (DDFS) has been encoded in VHDL and post simulation was carried out. The synthesized architecture exhibits a promising result of 90 dBc SFDR. The targeted structure is expected to show advantages for perceptible reduction of hardware resources and power consumption as well as high clock speeds.

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