A phase-locked loop reference spur modelling using simulink

Noorfazila Kamal, Said Al-Sarawi, Neil H E Weste, Derek Abbott

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.

Original languageEnglish
Title of host publication2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings
Pages279-283
Number of pages5
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010 - Kuala Lumpur
Duration: 12 Apr 201013 Apr 2010

Other

Other2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010
CityKuala Lumpur
Period12/4/1013/4/10

Fingerprint

Phase locked loops
Frequency synthesizers
Variable frequency oscillators
Transceivers
Transient analysis
Transistors
Pumps
Detectors
Bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kamal, N., Al-Sarawi, S., Weste, N. H. E., & Abbott, D. (2010). A phase-locked loop reference spur modelling using simulink. In 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings (pp. 279-283). [5503058] https://doi.org/10.1109/ICEDSA.2010.5503058

A phase-locked loop reference spur modelling using simulink. / Kamal, Noorfazila; Al-Sarawi, Said; Weste, Neil H E; Abbott, Derek.

2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. 2010. p. 279-283 5503058.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kamal, N, Al-Sarawi, S, Weste, NHE & Abbott, D 2010, A phase-locked loop reference spur modelling using simulink. in 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings., 5503058, pp. 279-283, 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010, Kuala Lumpur, 12/4/10. https://doi.org/10.1109/ICEDSA.2010.5503058
Kamal N, Al-Sarawi S, Weste NHE, Abbott D. A phase-locked loop reference spur modelling using simulink. In 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. 2010. p. 279-283. 5503058 https://doi.org/10.1109/ICEDSA.2010.5503058
Kamal, Noorfazila ; Al-Sarawi, Said ; Weste, Neil H E ; Abbott, Derek. / A phase-locked loop reference spur modelling using simulink. 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. 2010. pp. 279-283
@inproceedings{f95c036ce3464d588a088424d4f8b3ce,
title = "A phase-locked loop reference spur modelling using simulink",
abstract = "Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3{\%} error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.",
author = "Noorfazila Kamal and Said Al-Sarawi and Weste, {Neil H E} and Derek Abbott",
year = "2010",
doi = "10.1109/ICEDSA.2010.5503058",
language = "English",
isbn = "9781424466320",
pages = "279--283",
booktitle = "2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings",

}

TY - GEN

T1 - A phase-locked loop reference spur modelling using simulink

AU - Kamal, Noorfazila

AU - Al-Sarawi, Said

AU - Weste, Neil H E

AU - Abbott, Derek

PY - 2010

Y1 - 2010

N2 - Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.

AB - Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.

UR - http://www.scopus.com/inward/record.url?scp=77955286328&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955286328&partnerID=8YFLogxK

U2 - 10.1109/ICEDSA.2010.5503058

DO - 10.1109/ICEDSA.2010.5503058

M3 - Conference contribution

SN - 9781424466320

SP - 279

EP - 283

BT - 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings

ER -