A low power phase frequency detector for delay-locked loop

Lau Weng Loon, Md. Mamun Ibne Reaz, Khairun Nisa’ Minhad, Noorfazila Kamal, Wan Mimi Diyana Wan Zaki

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

High performance phase frequency detector (PFD) is one of the key modules in high speed delay-locked loop (DLL). The operation of DLL depends on the performance of its detector. The demand for the reduction of power dissipation in CMOS design is a challenge in order to optimize circuit power consumption. A low power dynamic pseudo-PMOS PFD is proposed to make DLL system more reliable. In this work NOR gate of typical TSPC PFD is replaced with a low power dissipation pseudo-PMOS AND gate built of 3 PMOS transistors. Pseudo-PMOS AND integrated into proposed TSPC PFD to run maximum frequency at 1G Hz with 1.8 V input power supply. This proposed PFD has been implemented in Mentor Graphics 0.18 μm CMOS process technology and consumed 163.36 μm<sup>2</sup> active layout area with 206 nW total power dissipation will further trim down the total cost of the DLL.

Original languageEnglish
Pages (from-to)391-397
Number of pages7
JournalJournal of Theoretical and Applied Information Technology
Volume74
Issue number3
Publication statusPublished - 2015

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Detector
Detectors
Dissipation
Energy dissipation
Power Consumption
Layout
Transistors
High Speed
Electric power utilization
High Performance
Optimise
Module
Networks (circuits)
Costs

Keywords

  • DLL
  • Dynamic PFD
  • Low noise PFD
  • Low power PFD
  • Pseudo-PMOS

ASJC Scopus subject areas

  • Computer Science(all)
  • Theoretical Computer Science

Cite this

A low power phase frequency detector for delay-locked loop. / Loon, Lau Weng; Ibne Reaz, Md. Mamun; Minhad, Khairun Nisa’; Kamal, Noorfazila; Wan Zaki, Wan Mimi Diyana.

In: Journal of Theoretical and Applied Information Technology, Vol. 74, No. 3, 2015, p. 391-397.

Research output: Contribution to journalArticle

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