A low power memoryless ROM design architecture for a direct digital frequency synthesizer

Salah Alkurwy, Sawal Hamid Md Ali, Md. Shabiul Islam, Faizul Idros

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput. However, this technique increases the number of registers as the pipeline stages increase. The shifted clocking technique is used to reduce the pipelined PA registers. The wave symmetry technique is applied to store (0: π/2) of the sine wave. The ROM is partitioned into three four-bit sub- ROMs based on the angular decomposition technique and trigonometric identity. A novel approach of memoryless ROM design technique is proposed and implemented in the design of a 24-bit DDFS system that replaces the conventional ROM. Replacing the memoryless sub- ROM circuits, instead of the conventional 12-bit ROM, reduces power consumption and area dimension. As a result, compared to the conventional ROM circuit, the values of area dimension and dynamic power are reduced by 15% and 14.8%, respectively.

Original languageEnglish
Pages (from-to)4023-4032
Number of pages10
JournalTurkish Journal of Electrical Engineering and Computer Sciences
Volume25
Issue number5
DOIs
Publication statusPublished - 1 Jan 2017

Fingerprint

Frequency synthesizers
ROM
Networks (circuits)
Electric power utilization
Pipelines
Throughput
Decomposition

Keywords

  • Carry look-ahead adder
  • Direct digital frequency synthesizer
  • Phase accumulator
  • Read-only memory

ASJC Scopus subject areas

  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

A low power memoryless ROM design architecture for a direct digital frequency synthesizer. / Alkurwy, Salah; Md Ali, Sawal Hamid; Islam, Md. Shabiul; Idros, Faizul.

In: Turkish Journal of Electrical Engineering and Computer Sciences, Vol. 25, No. 5, 01.01.2017, p. 4023-4032.

Research output: Contribution to journalArticle

@article{791c835e4c584a0da928f6c55689fb3a,
title = "A low power memoryless ROM design architecture for a direct digital frequency synthesizer",
abstract = "This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput. However, this technique increases the number of registers as the pipeline stages increase. The shifted clocking technique is used to reduce the pipelined PA registers. The wave symmetry technique is applied to store (0: π/2) of the sine wave. The ROM is partitioned into three four-bit sub- ROMs based on the angular decomposition technique and trigonometric identity. A novel approach of memoryless ROM design technique is proposed and implemented in the design of a 24-bit DDFS system that replaces the conventional ROM. Replacing the memoryless sub- ROM circuits, instead of the conventional 12-bit ROM, reduces power consumption and area dimension. As a result, compared to the conventional ROM circuit, the values of area dimension and dynamic power are reduced by 15{\%} and 14.8{\%}, respectively.",
keywords = "Carry look-ahead adder, Direct digital frequency synthesizer, Phase accumulator, Read-only memory",
author = "Salah Alkurwy and {Md Ali}, {Sawal Hamid} and Islam, {Md. Shabiul} and Faizul Idros",
year = "2017",
month = "1",
day = "1",
doi = "10.3906/elk-1609-61",
language = "English",
volume = "25",
pages = "4023--4032",
journal = "Turkish Journal of Electrical Engineering and Computer Sciences",
issn = "1300-0632",
publisher = "Turkiye Klinikleri",
number = "5",

}

TY - JOUR

T1 - A low power memoryless ROM design architecture for a direct digital frequency synthesizer

AU - Alkurwy, Salah

AU - Md Ali, Sawal Hamid

AU - Islam, Md. Shabiul

AU - Idros, Faizul

PY - 2017/1/1

Y1 - 2017/1/1

N2 - This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput. However, this technique increases the number of registers as the pipeline stages increase. The shifted clocking technique is used to reduce the pipelined PA registers. The wave symmetry technique is applied to store (0: π/2) of the sine wave. The ROM is partitioned into three four-bit sub- ROMs based on the angular decomposition technique and trigonometric identity. A novel approach of memoryless ROM design technique is proposed and implemented in the design of a 24-bit DDFS system that replaces the conventional ROM. Replacing the memoryless sub- ROM circuits, instead of the conventional 12-bit ROM, reduces power consumption and area dimension. As a result, compared to the conventional ROM circuit, the values of area dimension and dynamic power are reduced by 15% and 14.8%, respectively.

AB - This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput. However, this technique increases the number of registers as the pipeline stages increase. The shifted clocking technique is used to reduce the pipelined PA registers. The wave symmetry technique is applied to store (0: π/2) of the sine wave. The ROM is partitioned into three four-bit sub- ROMs based on the angular decomposition technique and trigonometric identity. A novel approach of memoryless ROM design technique is proposed and implemented in the design of a 24-bit DDFS system that replaces the conventional ROM. Replacing the memoryless sub- ROM circuits, instead of the conventional 12-bit ROM, reduces power consumption and area dimension. As a result, compared to the conventional ROM circuit, the values of area dimension and dynamic power are reduced by 15% and 14.8%, respectively.

KW - Carry look-ahead adder

KW - Direct digital frequency synthesizer

KW - Phase accumulator

KW - Read-only memory

UR - http://www.scopus.com/inward/record.url?scp=85041184186&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85041184186&partnerID=8YFLogxK

U2 - 10.3906/elk-1609-61

DO - 10.3906/elk-1609-61

M3 - Article

VL - 25

SP - 4023

EP - 4032

JO - Turkish Journal of Electrical Engineering and Computer Sciences

JF - Turkish Journal of Electrical Engineering and Computer Sciences

SN - 1300-0632

IS - 5

ER -