A high-speed and low-offset dynamic latch comparator

Labonnah Farzana Rahman, Md. Mamun Ibne Reaz, Chia Chieu Yin, Mohammad Marufuzzaman, Mohammad Anisur Rahman

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 m CMOS process show that the equivalent input-referred offset voltage is 720 V with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 W of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 m × 59.70 m.

Original languageEnglish
Article number258068
JournalScientific World Journal
Volume2014
DOIs
Publication statusPublished - 2014

Fingerprint

Flip flop circuits
topology
dissipation
Research
Energy dissipation
Electric potential
Comparator circuits
Topology
Coupled circuits
Networks (circuits)
Digital to analog conversion
Clocks
simulation
speed

ASJC Scopus subject areas

  • Biochemistry, Genetics and Molecular Biology(all)
  • Environmental Science(all)
  • Medicine(all)

Cite this

Rahman, L. F., Ibne Reaz, M. M., Yin, C. C., Marufuzzaman, M., & Rahman, M. A. (2014). A high-speed and low-offset dynamic latch comparator. Scientific World Journal, 2014, [258068]. https://doi.org/10.1155/2014/258068

A high-speed and low-offset dynamic latch comparator. / Rahman, Labonnah Farzana; Ibne Reaz, Md. Mamun; Yin, Chia Chieu; Marufuzzaman, Mohammad; Rahman, Mohammad Anisur.

In: Scientific World Journal, Vol. 2014, 258068, 2014.

Research output: Contribution to journalArticle

Rahman, Labonnah Farzana ; Ibne Reaz, Md. Mamun ; Yin, Chia Chieu ; Marufuzzaman, Mohammad ; Rahman, Mohammad Anisur. / A high-speed and low-offset dynamic latch comparator. In: Scientific World Journal. 2014 ; Vol. 2014.
@article{4cc42fcd287c4d919568ff0d059887bb,
title = "A high-speed and low-offset dynamic latch comparator",
abstract = "Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 m CMOS process show that the equivalent input-referred offset voltage is 720 V with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 W of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 m × 59.70 m.",
author = "Rahman, {Labonnah Farzana} and {Ibne Reaz}, {Md. Mamun} and Yin, {Chia Chieu} and Mohammad Marufuzzaman and Rahman, {Mohammad Anisur}",
year = "2014",
doi = "10.1155/2014/258068",
language = "English",
volume = "2014",
journal = "Scientific World Journal",
issn = "2356-6140",
publisher = "Hindawi Publishing Corporation",

}

TY - JOUR

T1 - A high-speed and low-offset dynamic latch comparator

AU - Rahman, Labonnah Farzana

AU - Ibne Reaz, Md. Mamun

AU - Yin, Chia Chieu

AU - Marufuzzaman, Mohammad

AU - Rahman, Mohammad Anisur

PY - 2014

Y1 - 2014

N2 - Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 m CMOS process show that the equivalent input-referred offset voltage is 720 V with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 W of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 m × 59.70 m.

AB - Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 m CMOS process show that the equivalent input-referred offset voltage is 720 V with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 W of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 m × 59.70 m.

UR - http://www.scopus.com/inward/record.url?scp=84904616252&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84904616252&partnerID=8YFLogxK

U2 - 10.1155/2014/258068

DO - 10.1155/2014/258068

M3 - Article

VL - 2014

JO - Scientific World Journal

JF - Scientific World Journal

SN - 2356-6140

M1 - 258068

ER -