A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

Tan Kok-Siang, Mohd Shahiman Sulaiman, Md. Mamun Ibne Reaz, Chuah Hean-Teik, Manoj Sachdev

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 μm CMOS process and occupies an active area of 0.2 × 0.32 mm 2. The CDR exhibits an RMS jitter of ± 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.

Original languageEnglish
Pages (from-to)101-109
Number of pages9
JournalAnalog Integrated Circuits and Signal Processing
Volume51
Issue number2
DOIs
Publication statusPublished - May 2007
Externally publishedYes

Fingerprint

Clock and data recovery circuits (CDR circuits)
Jitter
Detectors
Phase locked loops
Energy dissipation
Networks (circuits)

Keywords

  • Clock data recovery
  • CMOS analog integrated circuits
  • Half-rate CDR
  • Linear PD
  • PLL

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Signal Processing

Cite this

A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit. / Kok-Siang, Tan; Sulaiman, Mohd Shahiman; Ibne Reaz, Md. Mamun; Hean-Teik, Chuah; Sachdev, Manoj.

In: Analog Integrated Circuits and Signal Processing, Vol. 51, No. 2, 05.2007, p. 101-109.

Research output: Contribution to journalArticle

Kok-Siang, Tan ; Sulaiman, Mohd Shahiman ; Ibne Reaz, Md. Mamun ; Hean-Teik, Chuah ; Sachdev, Manoj. / A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit. In: Analog Integrated Circuits and Signal Processing. 2007 ; Vol. 51, No. 2. pp. 101-109.
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