A 5Gbit/s CMOS clock and data recovery circuit

Kok Siang Tan, Mohd Shahiman Sulaiman, Soon Hwei Tan, Md. Mamun Ibne Reaz, F. Mohd-Yasin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest. The circuit was designed in a 0.18-μm CMOS process and occupies an active area of 0.2 × 0.32 mm2. The CDR exhibits an RMS jitter of ±1.2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply.

Original languageEnglish
Title of host publication2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Pages415-418
Number of pages4
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC - Howloon
Duration: 19 Dec 200521 Dec 2005

Other

Other2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
CityHowloon
Period19/12/0521/12/05

Fingerprint

Clock and data recovery circuits (CDR circuits)
Jitter
Frequency bands
Energy dissipation
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Tan, K. S., Sulaiman, M. S., Tan, S. H., Ibne Reaz, M. M., & Mohd-Yasin, F. (2006). A 5Gbit/s CMOS clock and data recovery circuit. In 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC (pp. 415-418). [1635295] https://doi.org/10.1109/EDSSC.2005.1635295

A 5Gbit/s CMOS clock and data recovery circuit. / Tan, Kok Siang; Sulaiman, Mohd Shahiman; Tan, Soon Hwei; Ibne Reaz, Md. Mamun; Mohd-Yasin, F.

2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. 2006. p. 415-418 1635295.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tan, KS, Sulaiman, MS, Tan, SH, Ibne Reaz, MM & Mohd-Yasin, F 2006, A 5Gbit/s CMOS clock and data recovery circuit. in 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC., 1635295, pp. 415-418, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Howloon, 19/12/05. https://doi.org/10.1109/EDSSC.2005.1635295
Tan KS, Sulaiman MS, Tan SH, Ibne Reaz MM, Mohd-Yasin F. A 5Gbit/s CMOS clock and data recovery circuit. In 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. 2006. p. 415-418. 1635295 https://doi.org/10.1109/EDSSC.2005.1635295
Tan, Kok Siang ; Sulaiman, Mohd Shahiman ; Tan, Soon Hwei ; Ibne Reaz, Md. Mamun ; Mohd-Yasin, F. / A 5Gbit/s CMOS clock and data recovery circuit. 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. 2006. pp. 415-418
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