A 4.1-bit, 20 GS/s comparator for high speed flash ADC in 45 nm CMOS technology

M. J. Taghizadeh Marvast, Hilmi Sanusi, M. A. Mohd Ali

Research output: Contribution to journalArticle

Abstract

A 4.1-bit, high speed comparator for high-speed flash analog-to-digital converter and K-band applications that can work at a sampling rate of 20GS/s is presented in this paper. This fully differential comparator consists of three stages using a new structure to improve its performance. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The CMOS positive feedback and a new structure as output circuit are used to improve sampling rate and performance of comparator. The analyses and simulation results were obtained by using CMOS parameters. The comparator can operate with a 1 V peak to peak input range consuming 0.561 mW. The predicted performance is verified by analyses and simulations using HSPICE tool.

Original languageEnglish
Pages (from-to)538-541
Number of pages4
JournalInternational Review on Computers and Software
Volume6
Issue number4
Publication statusPublished - Jul 2011

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Sampling
Feedback
Digital to analog conversion
Networks (circuits)
Electric potential

Keywords

  • Analog to digital converter
  • Comparator
  • Preamplifier

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

A 4.1-bit, 20 GS/s comparator for high speed flash ADC in 45 nm CMOS technology. / Taghizadeh Marvast, M. J.; Sanusi, Hilmi; Mohd Ali, M. A.

In: International Review on Computers and Software, Vol. 6, No. 4, 07.2011, p. 538-541.

Research output: Contribution to journalArticle

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