4x4-Bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

This paper presents the simulation results of a 4x4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 μm standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition frequencies of 1 to 100 MHz, 4x4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

Original languageEnglish
Title of host publicationProceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
Pages364-368
Number of pages5
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 - Madrid
Duration: 27 Sep 201029 Sep 2010

Other

Other2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
CityMadrid
Period27/9/1029/9/10

Fingerprint

Digital devices
Smart sensors
Smart cards
Radio frequency identification (RFID)
Energy dissipation
Transistors
Electric power utilization
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Nayan, N. A., Takahashi, Y., & Sekine, T. (2010). 4x4-Bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. In Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 (pp. 364-368). [5642688] https://doi.org/10.1109/VLSISOC.2010.5642688

4x4-Bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. / Nayan, Nazrul Anuar; Takahashi, Yasuhiro; Sekine, Toshikazu.

Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010. 2010. p. 364-368 5642688.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nayan, NA, Takahashi, Y & Sekine, T 2010, 4x4-Bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. in Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010., 5642688, pp. 364-368, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010, Madrid, 27/9/10. https://doi.org/10.1109/VLSISOC.2010.5642688
Nayan NA, Takahashi Y, Sekine T. 4x4-Bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. In Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010. 2010. p. 364-368. 5642688 https://doi.org/10.1109/VLSISOC.2010.5642688
Nayan, Nazrul Anuar ; Takahashi, Yasuhiro ; Sekine, Toshikazu. / 4x4-Bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010. 2010. pp. 364-368
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