4-Bit ripple carry adder using two phase clocked adiabatic static CMOS logic

Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper demonstrates the low energy operation of 4-bit ripple carry adder (RCA) employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We evaluate NOT, NAND, XOR and NOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 μm CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. From the simulation results, we find that 4-bit 2PASCL RCA can save an average of 71.3% of dissipated energy as compared to that with a static 4-bit CMOS RCA at transition frequencies of 10 to 100 MHz. The results indicates that 2PASCL technology can be advantageously applied to low-power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

Original languageEnglish
Title of host publicationIEEE Region 10 Annual International Conference, Proceedings/TENCON
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 IEEE Region 10 Conference, TENCON 2009 - Singapore
Duration: 23 Nov 200926 Nov 2009

Other

Other2009 IEEE Region 10 Conference, TENCON 2009
CitySingapore
Period23/11/0926/11/09

Fingerprint

Adders
Diodes
Digital devices
Smart sensors
Smart cards
Logic gates
Logic circuits
SPICE
Radio frequency identification (RFID)
Electric power utilization
Topology
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

Nayan, N. A., Takahashi, Y., & Sekine, T. (2009). 4-Bit ripple carry adder using two phase clocked adiabatic static CMOS logic. In IEEE Region 10 Annual International Conference, Proceedings/TENCON [5396166] https://doi.org/10.1109/TENCON.2009.5396166

4-Bit ripple carry adder using two phase clocked adiabatic static CMOS logic. / Nayan, Nazrul Anuar; Takahashi, Yasuhiro; Sekine, Toshikazu.

IEEE Region 10 Annual International Conference, Proceedings/TENCON. 2009. 5396166.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nayan, NA, Takahashi, Y & Sekine, T 2009, 4-Bit ripple carry adder using two phase clocked adiabatic static CMOS logic. in IEEE Region 10 Annual International Conference, Proceedings/TENCON., 5396166, 2009 IEEE Region 10 Conference, TENCON 2009, Singapore, 23/11/09. https://doi.org/10.1109/TENCON.2009.5396166
Nayan NA, Takahashi Y, Sekine T. 4-Bit ripple carry adder using two phase clocked adiabatic static CMOS logic. In IEEE Region 10 Annual International Conference, Proceedings/TENCON. 2009. 5396166 https://doi.org/10.1109/TENCON.2009.5396166
Nayan, Nazrul Anuar ; Takahashi, Yasuhiro ; Sekine, Toshikazu. / 4-Bit ripple carry adder using two phase clocked adiabatic static CMOS logic. IEEE Region 10 Annual International Conference, Proceedings/TENCON. 2009.
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