4-Bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS

Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.

Original languageEnglish
Title of host publicationECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
Pages65-68
Number of pages4
DOIs
Publication statusPublished - 2009
Externally publishedYes
EventECCTD 2009 - European Conference on Circuit Theory and Design Conference Program - Antalya
Duration: 23 Aug 200927 Aug 2009

Other

OtherECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
CityAntalya
Period23/8/0927/8/09

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Adders
Energy dissipation
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Nayan, N. A., Takahashi, Y., & Sekine, T. (2009). 4-Bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. In ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program (pp. 65-68). [5274985] https://doi.org/10.1109/ECCTD.2009.5274985

4-Bit ripple carry adder of two-phase clocked adiabatic static CMOS logic : A comparison with static CMOS. / Nayan, Nazrul Anuar; Takahashi, Yasuhiro; Sekine, Toshikazu.

ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program. 2009. p. 65-68 5274985.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nayan, NA, Takahashi, Y & Sekine, T 2009, 4-Bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. in ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program., 5274985, pp. 65-68, ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, Antalya, 23/8/09. https://doi.org/10.1109/ECCTD.2009.5274985
Nayan NA, Takahashi Y, Sekine T. 4-Bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. In ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program. 2009. p. 65-68. 5274985 https://doi.org/10.1109/ECCTD.2009.5274985
Nayan, Nazrul Anuar ; Takahashi, Yasuhiro ; Sekine, Toshikazu. / 4-Bit ripple carry adder of two-phase clocked adiabatic static CMOS logic : A comparison with static CMOS. ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program. 2009. pp. 65-68
@inproceedings{a242e6f29f7a4a48b847219abeacd22f,
title = "4-Bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS",
abstract = "This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3{\%} lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.",
author = "Nayan, {Nazrul Anuar} and Yasuhiro Takahashi and Toshikazu Sekine",
year = "2009",
doi = "10.1109/ECCTD.2009.5274985",
language = "English",
isbn = "9781424438969",
pages = "65--68",
booktitle = "ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program",

}

TY - GEN

T1 - 4-Bit ripple carry adder of two-phase clocked adiabatic static CMOS logic

T2 - A comparison with static CMOS

AU - Nayan, Nazrul Anuar

AU - Takahashi, Yasuhiro

AU - Sekine, Toshikazu

PY - 2009

Y1 - 2009

N2 - This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.

AB - This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.

UR - http://www.scopus.com/inward/record.url?scp=71249093454&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=71249093454&partnerID=8YFLogxK

U2 - 10.1109/ECCTD.2009.5274985

DO - 10.1109/ECCTD.2009.5274985

M3 - Conference contribution

AN - SCOPUS:71249093454

SN - 9781424438969

SP - 65

EP - 68

BT - ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program

ER -